diff options
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 17 |
2 files changed, 10 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index f1e07412b7..e0d0b6074f 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -17,10 +17,6 @@ #include <soc/usb.h> #include <stdint.h> -#define MAX_HD_AUDIO_DMIC_LINKS 2 -#define MAX_HD_AUDIO_SNDW_LINKS 4 -#define MAX_HD_AUDIO_SSP_LINKS 6 - struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -117,10 +113,6 @@ struct soc_intel_alderlake_config { /* Audio related */ uint8_t PchHdaDspEnable; - uint8_t PchHdaAudioLinkHdaEnable; - uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; - uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; - uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; uint8_t PchHdaIDispLinkTmode; uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 385246734e..74d127ea98 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -131,13 +131,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchHdaEnable = is_dev_enabled(dev); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; - m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; - memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, - sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); - memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, - sizeof(m_cfg->PchHdaAudioLinkSspEnable)); - memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, - sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + /* + * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to + * configure GPIO pads for audio. Mainboard is expected to perform all GPIO + * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO + * configuration for audio pads. + */ + m_cfg->PchHdaAudioLinkHdaEnable = 0; + memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; |