diff options
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 60c149a72d..c956fd4826 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,13 +2,13 @@ chip soc/intel/alderlake device cpu_cluster 0 on end - register "power_limits_config[ADL_P_282_CORE]" = "{ + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_482_CORE]" = "{ + register "power_limits_config[ADL_P_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 90, @@ -20,7 +20,13 @@ chip soc/intel/alderlake .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_682_45W_CORE]" = "{ + register "power_limits_config[ADL_P_442_482_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 95, + .tdp_pl4 = 125, + }" + + register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, @@ -42,18 +48,6 @@ chip soc/intel/alderlake .tdp_pl4 = 68, }" - register "power_limits_config[ADL_P_242_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 123, - }" - - register "power_limits_config[ADL_P_442_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 95, - .tdp_pl4 = 125, - }" - # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |