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Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f22d1d4b87..522fe53560 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -130,6 +130,31 @@ config HEAP_SIZE hex default 0x10000 +# Intel recommends reserving the following resources per PCIe TBT root port, +# from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +config ADL_ENABLE_USB4_PCIE_RESOURCES + def_bool n + select PCIEXP_HOTPLUG + +if ADL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 + +endif # ADL_ENABLE_USB4_PCIE_RESOURCES + config MAX_PCH_ROOT_PORTS int default 10 if SOC_INTEL_ALDERLAKE_PCH_M |