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-rw-r--r--src/soc/amd/stoneyridge/include/soc/pci_devs.h6
-rw-r--r--src/soc/amd/stoneyridge/tsc_freq.c2
2 files changed, 1 insertions, 7 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index 865cf7170a..5fddc52dc5 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -145,12 +145,6 @@
#define PM_DEVID 0x15b4
#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC)
-#if !defined(__SIMPLE_DEVICE__)
- #include <device/device.h>
- #define DEV_D18F4 dev_find_slot(0, PM_DEVFN)
-#else
- #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)
-#endif
/* Northbridge Configuration */
#define NB_DEV 0x18
diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c
index 8c18884001..a8ed7c6a4c 100644
--- a/src/soc/amd/stoneyridge/tsc_freq.c
+++ b/src/soc/amd/stoneyridge/tsc_freq.c
@@ -36,7 +36,7 @@ unsigned long tsc_freq_mhz(void)
* to the "Software P-state Numbering" section, P0 is the highest
* non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
*/
- boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL)
+ boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
>> 2) & 0x7;
msr = rdmsr(PSTATE_0_MSR + boost_states);