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-rw-r--r--src/soc/amd/picasso/acpi/sb_pci0_fch.asl13
1 files changed, 4 insertions, 9 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index cbb1b91782..ed321f3e32 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/ioapic.h>
+
External(\_SB.ALIB, MethodObj)
/* System Bus */
@@ -71,16 +73,9 @@ Method(_CRS, 0) {
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
+ /* Declare memory between TOM1 and IOAPIC as available for PCI MMIO. */
MM1B = TOM1
- Local0 = 0x10000000 << 4
+ Local0 = IO_APIC_ADDR /* This is the first MMIO device after TOM1. */
Local0 -= TOM1
MM1L = Local0