diff options
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/msr.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/cpu_power_state.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/glinda/include/soc/msr.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/msr.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/include/soc/msr.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/msr.h | 2 |
6 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 83357c1884..5a0bac1231 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -4,8 +4,6 @@ #define AMD_CEZANNE_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c index dbda621141..9eb636d7d7 100644 --- a/src/soc/amd/common/block/acpi/cpu_power_state.c +++ b/src/soc/amd/common/block/acpi/cpu_power_state.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cpu/amd/msr.h> #include <cpu/x86/msr.h> -#include <soc/msr.h> #include <types.h> /* diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 5500ab5a07..51ab5851b1 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -6,8 +6,6 @@ #define AMD_GLINDA_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index 4b25195695..0fe4b6fcf0 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -4,8 +4,6 @@ #define AMD_MENDOCINO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 57001ad9d7..30ac560c3b 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -6,8 +6,6 @@ #define AMD_PHOENIX_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index ca6b25ac94..23926144c2 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -8,8 +8,6 @@ #define AMD_PICASSO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 |