diff options
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/sm.c | 9 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 5 |
4 files changed, 17 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index de1cb927ab..e723296ae4 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -382,4 +382,12 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 780a9e33d2..acdaa8a16e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -48,6 +48,10 @@ #define PM_SERIRQ_MODE BIT(6) #define PM_SERIRQ_ENABLE BIT(7) +#define PM_RTC_SHADOW 0x5b /* state when power resumes */ +#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */ +#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */ + #define PM_EVT_BLK 0x60 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define PCIEXPWAK_STS BIT(14) diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 21ce75b2ef..d4f428f343 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -27,15 +27,6 @@ #include <soc/southbridge.h> #include <soc/smbus.h> -#define NMI_OFF 0 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * The southbridge enables all USB controllers by default in SMBUS Control. * The southbridge enables SATA by default in SMBUS Control. diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d2495a6619..57bd3f08d2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -557,11 +557,16 @@ void southbridge_init(void *chip_info) void southbridge_final(void *chip_info) { + uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; + if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { agesawrapper_fchecfancontrolservice(); if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) enable_imc_thermal_zone(); } + if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) + restored_power = PM_RESTORE_S0_IF_PREV_S0; + pm_write8(PM_RTC_SHADOW, restored_power); } /* |