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-rw-r--r--src/soc/amd/cezanne/fsp_params.c8
-rw-r--r--src/soc/amd/picasso/fsp_params.c5
2 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c
index d3f9fcf555..b875dc02cb 100644
--- a/src/soc/amd/cezanne/fsp_params.c
+++ b/src/soc/amd/cezanne/fsp_params.c
@@ -2,6 +2,14 @@
#include <fsp/api.h>
+static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
+{
+ scfg->vbios_buffer_addr = 0;
+}
+
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
+ FSP_S_CONFIG *scfg = &supd->FspsConfig;
+
+ fsp_assign_vbios_upds(scfg);
}
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 2688b21a75..067ce2f280 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -175,7 +175,11 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff;
scfg->min_allowed_bl_level = cfg->min_allowed_bl_level;
}
+}
+static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
+{
+ scfg->vbios_buffer_addr = 0;
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
@@ -189,4 +193,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
fsp_assign_ioapic_upds(scfg);
fsp_usb_oem_customization(scfg, cfg);
fsp_edp_tuning_upds(scfg, cfg);
+ fsp_assign_vbios_upds(scfg);
}