diff options
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/lpc.c | 7 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ece78b625e..15c95813ee 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -213,8 +213,8 @@ #define SPI_FROM_USB_PREFETCH_EN BIT(23) #define LPC_HOST_CONTROL 0xbb -#define IMC_PAGE_FROM_HOST_EN BIT(0) -#define IMC_PORT_FROM_HOST_EN BIT(3) +#define PREFETCH_EN_SPI_FROM_HOST BIT(0) +#define T_START_ENH BIT(3) /* SPI Controller */ #define SPI_CNTRL0 0x00 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 4bf5a4f1b4..6833db6a8a 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -76,12 +76,11 @@ static void lpc_init(struct device *dev) pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* - * IMC is not used, but some of its registers and ports need to be - * programmed/accessed. So enable CPU access to them. This fixes - * SPI_CS# timing issue when running at 66MHz. + * Enable hand-instance of the pulse generator and SPI + * controller prefetch of flash. */ byte = pci_read_config8(dev, LPC_HOST_CONTROL); - byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN; + byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); |