diff options
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r-- | src/soc/amd/picasso/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/amd/picasso/i2c.c | 21 | ||||
-rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 27 |
3 files changed, 7 insertions, 42 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4567d5558b..ebcbd62068 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 40cf556b04..ebc833df2a 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -40,22 +40,13 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { - uint32_t pad_ctrl; + /* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this + configurable. */ + const struct i2c_pad_control ctrl = { + .rx_level = I2C_PAD_RX_3_3V, + }; - pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 2a3e38b43c..b8dd67b5c7 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -92,33 +92,6 @@ #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) -#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ |