diff options
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/agesa_acpi.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/data_fabric.h | 21 |
2 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 7482a03991..ed0b4569a4 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -64,10 +64,10 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, for (size_t dram_map_idx = 0; dram_map_idx < PICASSO_NUM_DRAM_REG; dram_map_idx++) { dram_base_reg = - data_fabric_read32(0, DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); + data_fabric_read32(DF_DRAM_BASE(dram_map_idx), IOMS0_FABRIC_ID); if (dram_base_reg & DRAM_BASE_REG_VALID) { - dram_limit_reg = data_fabric_read32(0, DF_DRAM_LIMIT(dram_map_idx), + dram_limit_reg = data_fabric_read32(DF_DRAM_LIMIT(dram_map_idx), IOMS0_FABRIC_ID); memory_length = ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 @@ -85,7 +85,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, } if (dram_base_reg & DRAM_BASE_HOLE_EN) { - dram_hole_ctl = data_fabric_read32(0, D18F0_DRAM_HOLE_CTL, + dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL, IOMS0_FABRIC_ID); hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); size_below_hole = hole_base - memory_base; diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 44463715d7..382de8a73e 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -3,20 +3,21 @@ #ifndef AMD_PICASSO_DATA_FABRIC_H #define AMD_PICASSO_DATA_FABRIC_H +#include <amdblocks/data_fabric_defs.h> #include <types.h> /* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define D18F0_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 +#define D18F0_MMIO_CTRL0 DF_REG_ID(0, 0x208) #define DF_MMIO_REG_SET_SIZE 4 #define DF_MMIO_REG_SET_COUNT 8 -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) #define IOMS0_FABRIC_ID 9 @@ -47,15 +48,15 @@ union df_ficaa { }; -#define D18F0_VGAEN 0x80 +#define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) -#define D18F0_DRAM_HOLE_CTL 0x104 +#define D18F0_DRAM_HOLE_CTL DF_REG_ID(0, 0x104) #define DRAM_HOLE_CTL_VALID BIT(0) #define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) -#define D18F0_DRAM_BASE0 0x110 +#define D18F0_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_INTLV_CH_SHFT 4 @@ -65,7 +66,7 @@ union df_ficaa { #define DRAM_BASE_ADDR_SHFT 12 #define DRAM_BASE_ADDR (0xfffff << DRAM_BASE_ADDR_SHFT) -#define D18F0_DRAM_LIMIT0 0x114 +#define D18F0_DRAM_LIMIT0 DF_REG_ID(0, 0x114) #define DRAM_LIMIT_DST_ID_SHFT 0 #define DRAM_LIMIT_DST_ID (0xff << DRAM_LIMIT_DST_ID_SHFT) #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 |