diff options
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 59 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fch.c (renamed from src/soc/amd/picasso/southbridge.c) | 52 |
3 files changed, 61 insertions, 55 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9c3720b1c3..6e1d88ba97 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -13,7 +13,7 @@ all-y += config.c bootblock-y += bootblock.c bootblock-y += aoac.c -bootblock-y += southbridge.c +bootblock-y += early_fch.c bootblock-y += i2c.c bootblock-y += uart.c bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c @@ -28,7 +28,6 @@ romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c romstage-y += aoac.c -romstage-y += southbridge.c romstage-y += psp.c romstage-y += mrc_cache.c @@ -49,7 +48,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += aoac.c -ramstage-y += southbridge.c +ramstage-y += fch.c ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c new file mode 100644 index 0000000000..f56a7585a4 --- /dev/null +++ b/src/soc/amd/picasso/early_fch.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/espi.h> +#include <amdblocks/lpc.h> +#include <amdblocks/smbus.h> +#include <amdblocks/spi.h> +#include <console/console.h> +#include <soc/i2c.h> +#include <soc/southbridge.h> +#include <soc/uart.h> +#include <types.h> + +static void lpc_configure_decodes(void) +{ + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) + lpc_enable_port80(); +} + +/* Before console init */ +void fch_pre_init(void) +{ + lpc_early_init(); + + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + lpc_configure_decodes(); + + fch_spi_early_init(); + enable_acpimmio_decode_pm04(); + fch_smbus_init(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); + enable_aoac_devices(); + sb_reset_i2c_slaves(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(PICASSO_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); +} + +/* After console init */ +void fch_early_init(void) +{ + fch_print_pmxc0_status(); + i2c_soc_early_init(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + espi_setup(); + espi_configure_decodes(); + } +} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/fch.c index 03c424ec6f..895a379c86 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/fch.c @@ -14,18 +14,13 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> -#include <amdblocks/espi.h> -#include <amdblocks/lpc.h> #include <amdblocks/acpi.h> -#include <amdblocks/smbus.h> -#include <amdblocks/spi.h> #include <amdblocks/smi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/smi.h> -#include <soc/uart.h> #include <soc/amd_pci_int_defs.h> #include <soc/pci_devs.h> #include <soc/nvs.h> @@ -100,53 +95,6 @@ void sb_clk_output_48Mhz(void) misc_write32(MISC_CLK_CNTL1, ctrl); } -static void lpc_configure_decodes(void) -{ - if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) - lpc_enable_port80(); -} - -/* Before console init */ -void fch_pre_init(void) -{ - lpc_early_init(); - - if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - lpc_configure_decodes(); - - fch_spi_early_init(); - enable_acpimmio_decode_pm04(); - fch_smbus_init(); - fch_enable_cf9_io(); - fch_enable_legacy_io(); - enable_aoac_devices(); - sb_reset_i2c_slaves(); - - /* - * On reset Range_0 defaults to enabled. We want to start with a clean - * slate to not have things unexpectedly enabled. - */ - clear_uart_legacy_config(); - - if (CONFIG(PICASSO_CONSOLE_UART)) - set_uart_config(CONFIG_UART_FOR_CONSOLE); -} - -/* After console init */ -void fch_early_init(void) -{ - fch_print_pmxc0_status(); - i2c_soc_early_init(); - - if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) - lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - espi_setup(); - espi_configure_decodes(); - } -} - void sb_enable(struct device *dev) { printk(BIOS_DEBUG, "%s\n", __func__); |