diff options
Diffstat (limited to 'src/soc/amd/picasso/acpi')
| -rw-r--r-- | src/soc/amd/picasso/acpi/acpi_wake_source.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/cpu.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/globalnvs.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/northbridge.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/pci_int.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_fch.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/sleepstates.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/soc.asl | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/usb.asl | 1 |
11 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/amd/picasso/acpi/acpi_wake_source.asl b/src/soc/amd/picasso/acpi/acpi_wake_source.asl index 9dadcdaf45..e847884073 100644 --- a/src/soc/amd/picasso/acpi/acpi_wake_source.asl +++ b/src/soc/amd/picasso/acpi/acpi_wake_source.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ Scope (\_SB) { diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index d8de75b4e0..c40ebf0968 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* Required function by EC, Notify OS to re-read CPU tables */ Method (PNOT) diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 672514bb0c..3ab35df630 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* This file is part of the coreboot project. */ /* * NOTE: The layout of the GNVS structure below must match the layout in diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 67ae6f2bbe..3227c7137a 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* Note: Only need HID on Primary Bus */ External (TOM1) diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 8f49751fc9..0f3d882a8b 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index eaa4563448..ecb54b9e16 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* PCI IRQ mapping registers, C00h-C01h. */ OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 5dd7159465..f8df3c059c 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 04e72c0a45..751c178762 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ External(\_SB.ALIB, MethodObj) diff --git a/src/soc/amd/picasso/acpi/sleepstates.asl b/src/soc/amd/picasso/acpi/sleepstates.asl index 9f4d999a41..88c6efc960 100644 --- a/src/soc/amd/picasso/acpi/sleepstates.asl +++ b/src/soc/amd/picasso/acpi/sleepstates.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Name(SSFG, 0x09) diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 790f89bdd8..b411c20ba4 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ Device(PCI0) { /* Describe the AMD Northbridge */ diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl index 2d3f4e24e6..f9021001b6 100644 --- a/src/soc/amd/picasso/acpi/usb.asl +++ b/src/soc/amd/picasso/acpi/usb.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ /* 0:12.0 - EHCI */ Device(EHC0) { |