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Diffstat (limited to 'src/soc/amd/picasso/acpi.c')
-rw-r--r--src/soc/amd/picasso/acpi.c39
1 files changed, 0 insertions, 39 deletions
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 2379d4347b..a6f1ebd4e4 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -11,7 +11,6 @@
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/amd/cpuid.h>
-#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
@@ -23,7 +22,6 @@
#include <amdblocks/ioapic.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
-#include <soc/msr.h>
#include <soc/southbridge.h>
#include <version.h>
#include "chip.h"
@@ -99,43 +97,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
}
-uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
-{
- uint32_t core_freq, core_freq_mul, core_freq_div;
- bool valid_freq_divisor;
-
- /* Core frequency multiplier */
- core_freq_mul = pstate_reg.cpu_fid_0_7;
-
- /* Core frequency divisor ID */
- core_freq_div = pstate_reg.cpu_dfs_id;
-
- if (core_freq_div == 0) {
- return 0;
- } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
- && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
- /* Allow 1/8 integer steps for this range */
- valid_freq_divisor = true;
- } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
- && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
- /* Only allow 1/4 integer steps for this range */
- valid_freq_divisor = true;
- } else {
- valid_freq_divisor = false;
- }
-
- if (valid_freq_divisor) {
- /* 25 * core_freq_mul / (core_freq_div / 8) */
- core_freq =
- ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
- } else {
- printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
- core_freq_div);
- core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
- }
- return core_freq;
-}
-
const acpi_cstate_t cstate_cfg_table[] = {
[0] = {
.ctype = 1,