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-rw-r--r--src/soc/amd/phoenix/acpi.c4
-rw-r--r--src/soc/amd/phoenix/include/soc/msr.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 4fae1c9d74..e3996ba869 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -153,8 +153,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID code 0x00 */
voltage_in_uvolts = 0;
} else {
- voltage_in_uvolts =
- SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
+ voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
+ (SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */
diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h
index ef7a2e2260..8eee0683ae 100644
--- a/src/soc/amd/phoenix/include/soc/msr.h
+++ b/src/soc/amd/phoenix/include/soc/msr.h
@@ -26,8 +26,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define SERIAL_VID_DECODE_MICROVOLTS 5000
-#define SERIAL_VID_BASE_MICROVOLTS 245000L
+#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
+#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24