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-rw-r--r--src/soc/amd/common/block/cpu/noncar/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/cpu/noncar/mpinit.c26
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index 27510bf540..3204667fc1 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -10,5 +10,6 @@ romstage-y += memmap.c
ramstage-y += cpu.c
romstage-y += cpu.c
ramstage-y += memmap.c
+ramstage-y += mpinit.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/mpinit.c b/src/soc/amd/common/block/cpu/noncar/mpinit.c
new file mode 100644
index 0000000000..002c50537f
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/mpinit.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <amdblocks/iomap.h>
+#include <console/console.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <device/device.h>
+#include <types.h>
+
+void mp_init_cpus(struct bus *cpu_bus)
+{
+ extern const struct mp_ops amd_mp_ops_with_smm;
+ if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
+ die_with_post_code(POSTCODE_HW_INIT_FAILURE,
+ "mp_init_with_smm failed. Halting.\n");
+
+ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+ mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
+ FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
+
+ /* SMMINFO only needs to be set up when booting from S5 */
+ if (!acpi_is_wakeup_s3())
+ apm_control(APM_CNT_SMMINFO);
+}