diff options
Diffstat (limited to 'src/soc/amd/common')
4 files changed, 47 insertions, 47 deletions
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 372f51517b..2bd3f5061e 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -28,7 +28,7 @@ _cache_as_ram_setup: .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -42,7 +42,7 @@ bootblock_pre_c_entry: pushl %eax /* tsc[31:0] */ before_carstage: - post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 72d778886a..eb556fabd0 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -7,7 +7,7 @@ .global bootblock_resume_entry bootblock_resume_entry: - post_code(POST_BOOTBLOCK_RESUME_ENTRY) + post_code(POSTCODE_BOOTBLOCK_RESUME_ENTRY) /* Get an early timestamp */ rdtsc @@ -24,7 +24,7 @@ bootblock_resume_entry: .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 #include <cpu/x86/64bit/entry64.inc> @@ -57,7 +57,7 @@ bootblock_pre_c_entry: pushl %eax /* tsc[31:0] */ #endif - post_code(POST_BOOTBLOCK_PRE_C_DONE) + post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h index 5251769731..10056e7b0a 100644 --- a/src/soc/amd/common/block/include/amdblocks/post_codes.h +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -3,31 +3,31 @@ #ifndef AMD_BLOCK_POST_CODES_H #define AMD_BLOCK_POST_CODES_H -#define POST_AGESA_AMDINITRESET 0x37 -#define POST_AGESA_AMDINITEARLY 0x38 +#define POSTCODE_AGESA_AMDINITRESET 0x37 +#define POSTCODE_AGESA_AMDINITEARLY 0x38 -#define POST_ROMSTAGE_MAIN 0x40 +#define POSTCODE_ROMSTAGE_MAIN 0x40 -#define POST_AGESA_AMDINITPOST 0x40 -#define POST_AGESA_AMDINITPOST_DONE 0x41 +#define POSTCODE_AGESA_AMDINITPOST 0x40 +#define POSTCODE_AGESA_AMDINITPOST_DONE 0x41 -#define POST_PSP_NOTIFY_DRAM 0x42 -#define POST_PSP_NOTIFY_DRAM_DONE 0x43 +#define POSTCODE_PSP_NOTIFY_DRAM 0x42 +#define POSTCODE_PSP_NOTIFY_DRAM_DONE 0x43 -#define POST_ROMSTAGE_RUN_POSTCAR 0x44 +#define POSTCODE_ROMSTAGE_RUN_POSTCAR 0x44 -#define POST_PSP_LOAD_SMU 0x46 -#define POST_AGESA_AMDINITENV 0x47 -#define POST_AGESA_AMDS3LATERESTORE 0x48 +#define POSTCODE_PSP_LOAD_SMU 0x46 +#define POSTCODE_AGESA_AMDINITENV 0x47 +#define POSTCODE_AGESA_AMDS3LATERESTORE 0x48 -#define POST_AGESA_AMDINITRESUME 0x60 -#define POST_AGESA_AMDINITRESUME_DONE 0x61 +#define POSTCODE_AGESA_AMDINITRESUME 0x60 +#define POSTCODE_AGESA_AMDINITRESUME_DONE 0x61 -#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90 +#define POSTCODE_BOOTBLOCK_SOC_EARLY_INIT 0x90 -#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 -#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0 -#define POST_BOOTBLOCK_PRE_C_DONE 0xa2 +#define POSTCODE_BOOTBLOCK_RESUME_ENTRY 0xb0 +#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POSTCODE_BOOTBLOCK_PRE_C_DONE 0xa2 #endif diff --git a/src/soc/amd/common/psp_verstage/include/psp_post_code.h b/src/soc/amd/common/psp_verstage/include/psp_post_code.h index 44464b6aa0..56b2a80c40 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_post_code.h +++ b/src/soc/amd/common/psp_verstage/include/psp_post_code.h @@ -3,33 +3,33 @@ #ifndef PSP_POST_CODE_H #define PSP_POST_CODE_H -#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00 -#define POSTCODE_CONSOLE_INIT 0x01 -#define POSTCODE_EARLY_INIT 0x02 -#define POSTCODE_LATE_INIT 0x03 -#define POSTCODE_VERSTAGE_MAIN 0x04 -#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 +#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00 +#define POSTCODE_CONSOLE_INIT 0x01 +#define POSTCODE_EARLY_INIT 0x02 +#define POSTCODE_LATE_INIT 0x03 +#define POSTCODE_VERSTAGE_MAIN 0x04 +#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 -#define POSTCODE_SAVE_BUFFERS 0x0E -#define POSTCODE_UPDATE_BOOT_REGION 0x0F +#define POSTCODE_SAVE_BUFFERS 0x0E +#define POSTCODE_UPDATE_BOOT_REGION 0x0F -#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 -#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 -#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 -#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3 -#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4 -#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 -#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6 -#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 -#define POSTCODE_FMAP_REGION_MISSING 0xC8 -#define POSTCODE_AMD_FW_MISSING 0xC9 -#define POSTCODE_CMOS_RECOVERY 0xCA -#define POSTCODE_EARLY_INIT_ERROR 0xCB -#define POSTCODE_INIT_TPM_FAILED 0xCC -#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD +#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 +#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 +#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 +#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3 +#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4 +#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 +#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6 +#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xC9 +#define POSTCODE_CMOS_RECOVERY 0xCA +#define POSTCODE_EARLY_INIT_ERROR 0xCB +#define POSTCODE_INIT_TPM_FAILED 0xCC +#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD -#define POSTCODE_UNMAP_SPI_ROM 0xF0 -#define POSTCODE_UNMAP_FCH_DEVICES 0xF1 -#define POSTCODE_LEAVING_VERSTAGE 0xF2 +#define POSTCODE_UNMAP_SPI_ROM 0xF0 +#define POSTCODE_UNMAP_FCH_DEVICES 0xF1 +#define POSTCODE_LEAVING_VERSTAGE 0xF2 #endif |