diff options
Diffstat (limited to 'src/soc/amd/common/block/spi')
-rw-r--r-- | src/soc/amd/common/block/spi/Makefile.inc | 9 | ||||
-rw-r--r-- | src/soc/amd/common/block/spi/fch_spi.c | 86 | ||||
-rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_ctrl.c | 2 |
3 files changed, 96 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index 0e706ef3cb..3d541b7052 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -9,4 +9,13 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-y += fch_spi_ctrl.c endif +bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += fch_spi.c +endif + endif diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c new file mode 100644 index 0000000000..950eee2947 --- /dev/null +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <amdblocks/chip.h> +#include <amdblocks/lpc.h> +#include <amdblocks/spi.h> +#include <arch/mmio.h> +#include <console/console.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t fch_spi_base(void) +{ + uintptr_t base; + + base = lpc_get_spibase(); + + if (base) + return base; + + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + + return SPI_BASE_ADDRESS; +} + +static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm) +{ + uintptr_t base = fch_spi_base(); + + write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm)); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); +} + +static void fch_spi_disable_4dw_burst(void) +{ + uintptr_t base = fch_spi_base(); + uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG)); + + write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST); +} + +static void fch_spi_set_read_mode(u32 mode) +{ + uintptr_t base = fch_spi_base(); + uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK; + + write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); +} + +static void fch_spi_config_mb_modes(void) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + + if (!cfg) + die("Common config structure is NULL!\n"); + + const struct spi_config *spi_cfg = &cfg->spi_config; + + fch_spi_set_read_mode(spi_cfg->read_mode); + fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, + spi_cfg->altio_speed, spi_cfg->tpm_speed); +} + +static void fch_spi_config_em100_modes(void) +{ + fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M); + fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +void fch_spi_config_modes(void) +{ + if (CONFIG(EM100)) + fch_spi_config_em100_modes(); + else + fch_spi_config_mb_modes(); +} + +void fch_spi_early_init(void) +{ + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + lpc_enable_spi_prefetch(); + fch_spi_disable_4dw_burst(); + fch_spi_config_modes(); +} diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index c0751a3f33..b048f1cbf7 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -2,9 +2,9 @@ #include <console/console.h> #include <spi_flash.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <amdblocks/lpc.h> +#include <amdblocks/spi.h> #include <device/pci_ops.h> #include <lib.h> #include <timer.h> |