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-rw-r--r--src/soc/amd/common/block/pm/Kconfig6
-rw-r--r--src/soc/amd/common/block/pm/Makefile.inc2
-rw-r--r--src/soc/amd/common/block/pm/chipset_state.c27
3 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/pm/Kconfig b/src/soc/amd/common/block/pm/Kconfig
index c976d017ec..e250bf0a2b 100644
--- a/src/soc/amd/common/block/pm/Kconfig
+++ b/src/soc/amd/common/block/pm/Kconfig
@@ -10,4 +10,10 @@ if SOC_AMD_COMMON_BLOCK_PM
config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
default y
+config SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
+ bool
+ help
+ Add common functionality to write CBMEM_ID_POWER_STATE for AMD
+ platforms that use FSP for hardware initialization.
+
endif # SOC_AMD_COMMON_BLOCK_PM
diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc
index f465e99ec1..f016a9db02 100644
--- a/src/soc/amd/common/block/pm/Makefile.inc
+++ b/src/soc/amd/common/block/pm/Makefile.inc
@@ -1 +1,3 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
+
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c
diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c
new file mode 100644
index 0000000000..3a4a0ba506
--- /dev/null
+++ b/src/soc/amd/common/block/pm/chipset_state.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/gpio_banks.h>
+#include <amdblocks/pmlib.h>
+#include <cbmem.h>
+#include <string.h>
+
+static struct chipset_power_state chipset_state;
+
+void fill_chipset_state(void)
+{
+ acpi_fill_pm_gpe_state(&chipset_state.gpe_state);
+ gpio_fill_wake_state(&chipset_state.gpio_state);
+}
+
+static void add_chipset_state_cbmem(int unused)
+{
+ struct chipset_power_state *state;
+
+ state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
+
+ if (state)
+ memcpy(state, &chipset_state, sizeof(*state));
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem);