diff options
Diffstat (limited to 'src/soc/amd/common/block/i2c')
| -rw-r--r-- | src/soc/amd/common/block/i2c/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i23c_pad_ctrl.c | 55 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i23c_pad_def.h | 64 | ||||
| -rw-r--r-- | src/soc/amd/common/block/i2c/i2c_pad_def.h | 2 |
5 files changed, 128 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 7c1ea0edd8..f10c14ab1f 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -8,3 +8,9 @@ config SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL help Select this option to add FCH I2C pad configuration functions to the build. + +config SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + bool + help + Select this option to add FCH I2C/I3C pad configuration functions to + the build. diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc index 3d2cdf6e09..b0747fe50f 100644 --- a/src/soc/amd/common/block/i2c/Makefile.inc +++ b/src/soc/amd/common/block/i2c/Makefile.inc @@ -1,2 +1,3 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c new file mode 100644 index 0000000000..36211a3264 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <types.h> +#include "i23c_pad_def.h" + +void fch_i23c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl) +{ + uint32_t pad_ctrl; + + pad_ctrl = misc_read32(MISC_I23C_PAD_CTRL(bus)); + + pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_I2C; + + switch (ctrl->rx_level) { + case I2C_PAD_RX_NO_CHANGE: + /* Default is enabled and thresholds for 1.8V operation */ + break; + case I2C_PAD_RX_OFF: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_OFF; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V; + break; + case I2C_PAD_RX_1_8V: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V; + break; + case I2C_PAD_RX_1_1V: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_1V; + break; + default: + printk(BIOS_WARNING, "Invalid I2C/I3C pad RX level for bus %u\n", bus); + break; + } + + pad_ctrl &= ~I23C_PAD_CTRL_FALLSLEW_SEL_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? + I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW; + + pad_ctrl &= I23C_PAD_CTRL_SLEW_N_MASK; + pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST; + + misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl); +} diff --git a/src/soc/amd/common/block/i2c/i23c_pad_def.h b/src/soc/amd/common/block/i2c/i23c_pad_def.h new file mode 100644 index 0000000000..8973a0c633 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i23c_pad_def.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_I23C_PAD_DEF_H +#define AMD_BLOCK_I23C_PAD_DEF_H + +#include <types.h> + +/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit + definitions. Which one is present depends on the SoC. */ +#define MISC_I23C0_PAD_CTRL 0xd8 +#define MISC_I23C_PAD_CTRL(bus) (MISC_I23C0_PAD_CTRL + 4 * (bus)) + +#define I23C_PAD_CTRL_OD_RP_SW_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define I23C_PAD_CTRL_OD_RP_SW_SHIFT 0 +#define I23C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) +#define I23C_PAD_CTRL_RX_SHIFT 4 +#define I23C_PAD_CTRL_RX_SEL_OFF (0 << I23C_PAD_CTRL_RX_SHIFT) +#define I23C_PAD_CTRL_RX_SEL_ON (3 << I23C_PAD_CTRL_RX_SHIFT) +#define I23C_PAD_CTRL_SLEW_N_MASK (BIT(6) | BIT(7)) +#define I23C_PAD_CTRL_SLEW_N_SHIFT 7 +#define I23C_PAD_CTRL_SLEW_N_DIS (0 << I23C_PAD_CTRL_SLEW_N_SHIFT) +#define I23C_PAD_CTRL_SLEW_N_FAST (3 << I23C_PAD_CTRL_SLEW_N_SHIFT) +#define I23C_PAD_CTRL_FALLSLEW_SEL_MASK (BIT(8) | BIT(9)) +#define I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT 8 +#define I23C_PAD_CTRL_FALLSLEW_SEL_STD (0 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT) +#define I23C_PAD_CTRL_FALLSLEW_SEL_LOW (3 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT) +#define I23C_PAD_CTRL_SPIKE_RC_EN_MASK (BIT(10) | BIT(11)) +#define I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT 10 +#define I23C_PAD_CTRL_SPIKE_RC_DIS (0 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT) +#define I23C_PAD_CTRL_SPIKE_RC_EN (3 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT) +#define I23C_PAD_CTRL_CAP_DOWN BIT(12) +#define I23C_PAD_CTRL_CAP_UP BIT(13) +#define I23C_PAD_CTRL_RES_DOWN BIT(14) +#define I23C_PAD_CTRL_RES_UP BIT(15) +#define I23C_PAD_CTRL_BIAS_CRT_EN_MASK (BIT(16) | BIT(17)) +#define I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT 16 +#define I23C_PAD_CTRL_BIAS_CRT_DIS (0 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT) +#define I23C_PAD_CTRL_BIAS_CRT_EN (3 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT) +#define I23C_PAD_CTRL_SPARE0 BIT(18) +#define I23C_PAD_CTRL_SPARE1 BIT(19) +#define I23C_PAD_CTRL_COMP_SEL0 BIT(20) /* unused */ +#define I23C_PAD_CTRL_COMP_SEL1 BIT(21) /* unused */ +#define I23C_PAD_CTRL_RES_BIAS_EN_MASK (BIT(22) | BIT(23)) +#define I23C_PAD_CTRL_RES_BIAS_EN_SHIFT 22 +#define I23C_PAD_CTRL_RES_BIAS_T_COMP (0 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT) +#define I23C_PAD_CTRL_RES_BIAS_CONST_GM (3 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT) +#define I23C_PAD_CTRL_SLEW_P_MASK (BIT(24) | BIT(25)) +#define I23C_PAD_CTRL_SLEW_P_SHIFT 24 +#define I23C_PAD_CTRL_SLEW_P_DIS (0 << I23C_PAD_CTRL_SLEW_P_SHIFT) +#define I23C_PAD_CTRL_SLEW_P_EN (3 << I23C_PAD_CTRL_SLEW_P_SHIFT) +#define I23C_PAD_CTRL_MODE_I3C_I2C_MASK (BIT(26) | BIT(27)) +#define I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT 26 +#define I23C_PAD_CTRL_MODE_I2C (0 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT) +#define I23C_PAD_CTRL_MODE_I3C (3 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT) +#define I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK (BIT(28) | BIT(29)) +#define I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT 28 +#define I23C_PAD_CTRL_MODE_1_1V (0 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT) +#define I23C_PAD_CTRL_MODE_1_8V (3 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT) +#define I23C_PAD_CTRL_SPIKE_C_SEL_MASK (BIT(30) | BIT(31)) +#define I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT 30 +#define I23C_PAD_CTRL_SPIKE_C_SEL_DIS (0 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT) +#define I23C_PAD_CTRL_SPIKE_C_SEL_EN (3 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT) + +#endif /* AMD_BLOCK_I23C_PAD_DEF_H */ diff --git a/src/soc/amd/common/block/i2c/i2c_pad_def.h b/src/soc/amd/common/block/i2c/i2c_pad_def.h index 76e10cd545..5e699b1411 100644 --- a/src/soc/amd/common/block/i2c/i2c_pad_def.h +++ b/src/soc/amd/common/block/i2c/i2c_pad_def.h @@ -5,6 +5,8 @@ #include <types.h> +/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit + definitions. Which one is present depends on the SoC. */ #define MISC_I2C0_PAD_CTRL 0xd8 #define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) |