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-rw-r--r--src/soc/amd/cezanne/acpi/pci0.asl3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index f9c732f9b0..f9956b68c5 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -78,4 +78,7 @@ Device(PCI0) {
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
+ /* 0:14.3 - LPC */
+ #include <soc/amd/common/acpi/lpc.asl>
+
} /* End PCI0 scope */