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-rw-r--r--src/soc/amd/cezanne/psp_verstage/chipset.c10
-rw-r--r--src/soc/amd/cezanne/psp_verstage/svc.c7
2 files changed, 7 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c
index 30f613a492..41d318e0eb 100644
--- a/src/soc/amd/cezanne/psp_verstage/chipset.c
+++ b/src/soc/amd/cezanne/psp_verstage/chipset.c
@@ -40,13 +40,3 @@ void platform_report_mode(int developer_mode_enabled)
else
svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION);
}
-
-
-/* Functions below are stub functions for not-yet-implemented PSP features.
- * These functions should be replaced with proper implementations later.
- */
-
-uint32_t svc_write_postcode(uint32_t postcode)
-{
- return 0;
-}
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c
index 78f71260a4..12fccc38f7 100644
--- a/src/soc/amd/cezanne/psp_verstage/svc.c
+++ b/src/soc/amd/cezanne/psp_verstage/svc.c
@@ -140,3 +140,10 @@ uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode)
SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval);
return retval;
}
+
+uint32_t svc_write_postcode(uint32_t postcode)
+{
+ uint32_t retval = 0;
+ SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval);
+ return retval;
+}