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-rw-r--r--src/soc/amd/cezanne/Kconfig23
1 files changed, 1 insertions, 22 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ca84b33f06..452e3ec354 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -58,6 +58,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
+ select SOC_AMD_COMMON_BLOCK_PSP_SPL
select SOC_AMD_COMMON_BLOCK_RESET
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
@@ -376,28 +377,6 @@ config PSP_WHITELIST_FILE
depends on HAVE_PSP_WHITELIST_FILE
default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
-config PERFORM_SPL_FUSING
- bool "Send SPL fuse command to PSP"
- default n
- help
- Send the Security Patch Level (SPL) fusing command to the PSP in
- order to update the minimum SPL version to be written to the SoC's
- fuse bits. This will prevent using any embedded firmware components
- with lower SPL version.
-
- If unsure, answer 'n'
-
-config SPL_TABLE_FILE
- string "SPL table file override"
- help
- Provide a mainboard-specific Security Patch Level (SPL) table file
- override. The SPL file is required to support PSP FW anti-rollback
- and needs to be created by AMD. The default SPL file specified in the
- SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule
- and applies to all boards that use the SoC without verstage on PSP.
- In the verstage on PSP case, a different SPL file is specific as an
- override via this Kconfig option.
-
config PSP_SOFTFUSE_BITS
string "PSP Soft Fuse bits to enable"
default "28 6"