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-rw-r--r--src/northbridge/amd/pi/Makefile.inc3
-rw-r--r--src/northbridge/amd/pi/ramtop.c33
2 files changed, 0 insertions, 36 deletions
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index ffafc6038f..61917c9d48 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
-romstage-y += ramtop.c
-postcar-y += ramtop.c
-ramstage-y += ramtop.c
endif
diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c
deleted file mode 100644
index 823a15c079..0000000000
--- a/src/northbridge/amd/pi/ramtop.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include <cbmem.h>
-
-#define CBMEM_TOP_SCRATCHPAD 0x78
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
- uint16_t top_cache = ramtop >> 16;
- pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- uint16_t top_cache;
- top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD);
- return (top_cache << 16);
-}