diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 11 | ||||
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.h | 2 |
3 files changed, 8 insertions, 7 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index c1b22a28a0..a434307035 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -4,6 +4,7 @@ #define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ #define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#if 0 static unsigned int calibrate_tsc(void) { /* Set the Gate high, disable speaker */ @@ -64,6 +65,7 @@ bad_ctc: print_err("bad_ctc\n"); return 0; } +#endif /* spll_raw_clk = SYSREF * FbDIV, * GLIU Clock = spll_raw_clk / MDIV diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 3f99cab8ee..c8f248d55c 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -102,17 +102,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) msr.lo = 0x8ea0ad6a; wrmsr(0x4c00000f, msr); - /* Fixes from Jordan Crouse of AMD. */ - - /* make sure there is nothing stale in the cache */ - __asm__("wbinvd\n"); - - print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ + /* Note: The descriptor needs to be enabled to point at memory */ volatile unsigned long *ptr; - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } + print_info("RAM DLL lock\n"); + } diff --git a/src/northbridge/amd/gx2/raminit.h b/src/northbridge/amd/gx2/raminit.h index f13f53a09f..a49bf20886 100644 --- a/src/northbridge/amd/gx2/raminit.h +++ b/src/northbridge/amd/gx2/raminit.h @@ -7,4 +7,6 @@ struct mem_controller { uint16_t channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif /* RAMINIT_H */ |