diff options
Diffstat (limited to 'src/northbridge')
4 files changed, 7 insertions, 20 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index bc1a1c8df1..d0faa7931c 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -182,11 +182,6 @@ Device (PDRC) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif }) // Current Resource Settings diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 61ad23610e..c00c801ee1 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -14,6 +14,7 @@ #include <boot/tables.h> #include <security/intel/txt/txt_register.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" #include "haswell.h" @@ -335,11 +336,9 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif + if (CONFIG(CHROMEOS_RAMOOPS)) + chromeos_reserve_ram_oops(dev, index++); + *resource_cnt = index; } diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 5d7a777803..cf1d61ce9f 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -20,11 +20,6 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - /* Required for SandyBridge sighting 3715511 */ Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 22743553d9..ead3c67c0d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -14,6 +14,7 @@ #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm_reloc.h> +#include <vendorcode/google/chromeos/chromeos.h> /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -67,11 +68,8 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif + if (CONFIG(CHROMEOS_RAMOOPS)) + chromeos_reserve_ram_oops(dev, index++); if (is_sandybridge()) { /* Required for SandyBridge sighting 3715511 */ |