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-rw-r--r--src/northbridge/intel/gm45/raminit_meminfo.c12
-rw-r--r--src/northbridge/intel/haswell/broadwell_mrc/raminit.c12
-rw-r--r--src/northbridge/intel/haswell/haswell_mrc/raminit.c12
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c2
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c24
5 files changed, 31 insertions, 31 deletions
diff --git a/src/northbridge/intel/gm45/raminit_meminfo.c b/src/northbridge/intel/gm45/raminit_meminfo.c
index c2c7f510d8..9fd4065ffc 100644
--- a/src/northbridge/intel/gm45/raminit_meminfo.c
+++ b/src/northbridge/intel/gm45/raminit_meminfo.c
@@ -24,14 +24,14 @@ static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx)
static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx)
{
const u8 addr = sysinfo->spd_map[idx];
- for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) {
- dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k);
+ for (int k = 0; k < SPD_DDR3_SERIAL_LEN; k++) {
+ dimm->serial[k] = smbus_read_byte(addr, SPD_DDR3_SERIAL_NUM + k);
}
- for (int k = 0; k < SPD_DIMM_PART_LEN; k++) {
- dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k);
+ for (int k = 0; k < SPD_DDR3_PART_LEN; k++) {
+ dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DDR3_PART_NUM + k);
}
- dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) |
- (smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0);
+ dimm->mod_id = (smbus_read_byte(addr, SPD_DDR3_MOD_ID2) << 8) |
+ (smbus_read_byte(addr, SPD_DDR3_MOD_ID1) << 0);
}
static u32 get_mem_clock_mt(const int clock_index)
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index e7e9b634c8..7af21f578a 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -219,14 +219,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = slot;
dimm->bank_locator = ch * 2;
memcpy(dimm->serial,
- &pei_data->spd_data[ch][slot][SPD_DIMM_SERIAL_NUM],
- SPD_DIMM_SERIAL_LEN);
+ &pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM],
+ SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number,
- &pei_data->spd_data[ch][slot][SPD_DIMM_PART_NUM],
- SPD_DIMM_PART_LEN);
+ &pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM],
+ SPD_DDR3_PART_LEN);
dimm->mod_id =
- (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID2] << 8) |
- (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID1] & 0xff);
+ (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) |
+ (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 7109e46da0..d97ab2a8ac 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -252,14 +252,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = d_num;
dimm->bank_locator = ch * 2;
memcpy(dimm->serial,
- &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM],
- SPD_DIMM_SERIAL_LEN);
+ &pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM],
+ SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number,
- &pei_data->spd_data[index][SPD_DIMM_PART_NUM],
- SPD_DIMM_PART_LEN);
+ &pei_data->spd_data[index][SPD_DDR3_PART_NUM],
+ SPD_DDR3_PART_LEN);
dimm->mod_id =
- (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
- (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
+ (pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) |
+ (pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2a4eae5bd5..8a8bd8310b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -142,7 +142,7 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
{
int j;
if (id_only) {
- for (j = SPD_DIMM_MOD_ID1; j < 128; j++)
+ for (j = SPD_DDR3_MOD_ID1; j < 128; j++)
(*spd)[j] = smbus_read_byte(addr, j);
} else {
for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index cad86ba51e..8d3c4023c8 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -467,14 +467,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 0;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
- &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
- sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
+ &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
+ sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
- &pei_data->spd_data[0][SPD_DIMM_PART_NUM],
- sizeof(uint8_t) * SPD_DIMM_PART_LEN);
+ &pei_data->spd_data[0][SPD_DDR3_PART_NUM],
+ sizeof(uint8_t) * SPD_DDR3_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
- (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
- (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
+ (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
+ (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
@@ -491,14 +491,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 1;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
- &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
- sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
+ &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM],
+ sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
- &pei_data->spd_data[0][SPD_DIMM_PART_NUM],
- sizeof(uint8_t) * SPD_DIMM_PART_LEN);
+ &pei_data->spd_data[0][SPD_DDR3_PART_NUM],
+ sizeof(uint8_t) * SPD_DDR3_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
- (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
- (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
+ (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) |
+ (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF);
dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:30:17 +0000