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-rw-r--r--src/northbridge/intel/i945/early_init.c3
-rw-r--r--src/northbridge/intel/i945/raminit.c20
2 files changed, 13 insertions, 10 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 0a2c99e51e..45501d1f53 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -939,7 +939,8 @@ void i945_late_initialization(int s3resume)
i945_setup_dmi_rcrb();
- i945_setup_pci_express_x16();
+ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ i945_setup_pci_express_x16();
i945_setup_root_complex_topology();
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0499b48ee9..1f07425d6c 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2576,17 +2576,19 @@ static void sdram_power_management(struct sys_info *sysinfo)
reg32 |= (1 << 12) | (1 << 11);
MCHBAR32(C1DRC1) = reg32;
- if (i945_silicon_revision() > 1) {
- /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
- u16 peg_bits = (1 << 5) | (1 << 0);
+ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
+ if (i945_silicon_revision() > 1) {
+ /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
+ u16 peg_bits = (1 << 5) | (1 << 0);
- MCHBAR16(UPMC1) = 0x1010 | peg_bits;
- } else {
- /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
- u16 peg_bits = (1 << 5) | (1 << 0);
+ MCHBAR16(UPMC1) = 0x1010 | peg_bits;
+ } else {
+ /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
+ u16 peg_bits = (1 << 5) | (1 << 0);
- /* Rev 0 and 1 */
- MCHBAR16(UPMC1) = 0x0010 | peg_bits;
+ /* Rev 0 and 1 */
+ MCHBAR16(UPMC1) = 0x0010 | peg_bits;
+ }
}
reg16 = MCHBAR16(UPMC2);