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-rw-r--r--src/northbridge/via/cx700/lpc.c4
-rw-r--r--src/northbridge/via/vx800/lpc.c8
-rw-r--r--src/northbridge/via/vx800/northbridge.c2
-rw-r--r--src/northbridge/via/vx800/uma_ram_setting.c2
-rw-r--r--src/northbridge/via/vx900/northbridge.c2
5 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index ece05b10f3..2d7431628f 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -203,7 +203,7 @@ static void cx700_set_lpc_registers(struct device *dev)
enables |= 1 << 3;
pci_write_config8(dev, 0x4d, enables);
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+ /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
@@ -220,7 +220,7 @@ static void cx700_set_lpc_registers(struct device *dev)
// Power management setup
setup_pm(dev);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
/* Enable HPET timer */
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 25ceed12bb..00c199971c 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -269,7 +269,7 @@ static void vx800_sb_init(struct device *dev)
enables |= 0x41; //
pci_write_config8(dev, 0x58, enables);
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+ /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
@@ -283,7 +283,7 @@ static void vx800_sb_init(struct device *dev)
// Power management setup
setup_pm(dev);
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+ /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
@@ -329,14 +329,14 @@ static void southbridge_init(struct device *dev)
S3_usb_wakeup(dev);
S3_lid_wakeup(dev);
-/* enable acpi cpu c3 state. (c2 state need not do anything.)
+/* enable acpi CPU c3 state. (c2 state need not do anything.)
#1
fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
fadt->p_lvl2_lat = 0x50; //this is the coreboot source
fadt->p_lvl3_lat = 0x320;//
fadt->pm2_cnt_len = 1;//to support cpu-c3
#2
- ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
+ ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
#3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
1 enable SLP# asserts in C3 state PMIORx26<1> =1
2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1
diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c
index 4925b53bb5..639132132f 100644
--- a/src/northbridge/via/vx800/northbridge.c
+++ b/src/northbridge/via/vx800/northbridge.c
@@ -70,7 +70,7 @@ static const struct pci_driver memctrl_driver __pci_driver = {
static void pci_domain_set_resources(device_t dev)
{
/*
- * the order is important to find the correct ram size.
+ * the order is important to find the correct RAM size.
*/
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t mc_dev;
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index dc3ab39d1b..1aa0967e26 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -168,7 +168,7 @@ void SetUMARam(void)
Tmp = VIACONFIG_VGA_PCI_14;
pci_write_config32(vga_dev, 0x14, Tmp);
- //enable direct cpu frame buffer access
+ //enable direct CPU frame buffer access
i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1);
i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i);
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 368ff8cb5f..32bb539812 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -259,7 +259,7 @@ static void vx900_set_resources(device_t dev)
tolmk = MIN(full_tolmk, tomk);
tolmk -= fbufk;
ram_resource(dev, idx++, 0, 640);
- printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10);
+ printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10);
/* FIXME: how can we avoid leaving this hole?
* Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */
/* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem