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-rw-r--r--src/northbridge/via/vt8623/northbridge.c12
-rw-r--r--src/northbridge/via/vt8623/raminit.c34
-rw-r--r--src/northbridge/via/vt8623/vga.c8
3 files changed, 27 insertions, 27 deletions
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 4920ec3973..7ba9cd6316 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -21,7 +21,7 @@
* Apparently these registers govern some sort of bus master behavior.
*/
-static void northbridge_init(device_t dev)
+static void northbridge_init(device_t dev)
{
device_t fb_dev;
unsigned long fb;
@@ -40,7 +40,7 @@ static void northbridge_init(device_t dev)
pci_write_config8(dev, 0x84, 0x80);
pci_write_config16(dev, 0x80, 0x610f);
pci_write_config32(dev, 0x88, 0x00000002);
-
+
fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
if (fb_dev) {
/* Fixup GART and framebuffer addresses properly.
@@ -168,16 +168,16 @@ static void pci_domain_set_resources(device_t dev)
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
- /* these are ENDING addresses, not sizes.
+ /* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
- * So we just take the max, that gives us total.
+ * So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
- printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
+ printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
@@ -210,7 +210,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
-};
+};
static void cpu_bus_init(device_t dev)
{
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index f57127b3da..295011b785 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*
+/*
Automatically detect and set up ddr dram on the CLE266 chipset.
Assumes DDR memory, though chipset also supports SDRAM
Assumes at least 266Mhz memory as no attempt is made to clock
@@ -35,9 +35,9 @@
-void dimm_read(unsigned long bank,unsigned long x)
+void dimm_read(unsigned long bank,unsigned long x)
{
- //unsigned long eax;
+ //unsigned long eax;
volatile unsigned long y;
//eax = x;
y = * (volatile unsigned long *) (x+ bank) ;
@@ -46,7 +46,7 @@ void dimm_read(unsigned long bank,unsigned long x)
void
-dumpnorth(device_t north)
+dumpnorth(device_t north)
{
uint16_t r, c;
for(r = 0; r < 256; r += 16) {
@@ -65,7 +65,7 @@ void print_val(char *str, int val)
print_debug_hex8(val);
}
-static void ddr_ram_setup(const struct mem_controller *ctrl)
+static void ddr_ram_setup(const struct mem_controller *ctrl)
{
device_t north = (device_t) 0;
uint8_t b, c, bank;
@@ -75,7 +75,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
print_debug("vt8623 init starting\n");
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
-
+
pci_write_config8(north,0x75,0x08);
@@ -105,7 +105,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
print_val("Detecting Memory\nNumber of Banks ",b);
if( b != 2 ){ // not 16 Mb type
-
+
/*
Read SPD byte 3, Number of row addresses.
*/
@@ -126,7 +126,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
64/128Mb chip
Read SPD byte 4, Number of column addresses.
-*/
+*/
b = smbus_read_byte(0xa0,4);
print_val("\nNo Columns ",b);
if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
@@ -153,7 +153,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
if( b & 0x02 ) c = 0x80; // 2GB
else if( b & 0x01) c = 0x40; // 1GB
else if( b & 0x80) c = 0x20; // 512Mb
- else if( b & 0x40) c = 0x10; // 256Mb
+ else if( b & 0x40) c = 0x10; // 256Mb
else if( b & 0x20) c = 0x08; // 128Mb
else if( b & 0x10) c = 0x04; // 64Mb
else if( b & 0x08) c = 0x02; // 32Mb
@@ -191,7 +191,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
-
+
if( b & 0x10 ){ // DDR offering optional CAS 3
print_debug("\nStarting at CAS 3");
@@ -405,7 +405,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
/* MSR Enable */
pci_write_config8(north,0x6b,0x13);
-/*
+/*
Mode Register Definition
with adjustement so that address calculation is correct - 64 bit technology, therefore
a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
@@ -414,9 +414,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
MR[9-7] CAS Latency
MR[6] Burst Type 0 = sequential, 1 = interleaved
MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
- MR[0-2] dont care
+ MR[0-2] dont care
- CAS Latency
+ CAS Latency
000 reserved
001 reserved
010 2
@@ -498,10 +498,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
// if everything verified then found low bond
break;
-
+
}
- print_val("\nLow Bond ",i);
- if( i < 0xff ){
+ print_val("\nLow Bond ",i);
+ if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
pci_write_config8(north,0x68,i ^ (i>>1) );
@@ -588,7 +588,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0x71,0xc8);
-
+
/* graphics aperture base */
diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c
index 7dbb7831b1..78ffe0aa94 100644
--- a/src/northbridge/via/vt8623/vga.c
+++ b/src/northbridge/via/vt8623/vga.c
@@ -57,7 +57,7 @@ static int via_vt8623_int15_handler(struct eregs *regs)
case 0x5f02:
regs->eax=0x5f;
regs->ebx= (regs->ebx & 0xffff0000) | 2;
- regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
+ regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default
res=0;
break;
@@ -65,7 +65,7 @@ static int via_vt8623_int15_handler(struct eregs *regs)
regs->eax=0x860f;
break;
default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
regs->eax & 0xffff);
break;
}
@@ -122,11 +122,11 @@ static void vga_init(device_t dev)
// call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
// this is how it looks:
vga_enable_console();
-
+
#ifdef MEASURE_VGA_INIT_TIME
clocks2 = rdmsr(0x10);
instructions = rdmsr(0xc2);
-
+
printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 06:17:28 +0000