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-rw-r--r--src/northbridge/intel/ironlake/chip.h5
-rw-r--r--src/northbridge/intel/ironlake/raminit.c19
2 files changed, 1 insertions, 23 deletions
diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h
index b2976bced5..ab589ea221 100644
--- a/src/northbridge/intel/ironlake/chip.h
+++ b/src/northbridge/intel/ironlake/chip.h
@@ -34,11 +34,6 @@ struct northbridge_intel_ironlake_config {
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
struct i915_gpu_controller_info gfx;
-
- /*
- * Maximum PCI mmio size in MiB.
- */
- u16 pci_mmio_size;
};
#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index f073ddae89..34e56571ca 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1273,23 +1273,6 @@ static void program_board_delay(struct raminfo *info)
}
#define DEFAULT_PCI_MMIO_SIZE 2048
-#define HOST_BRIDGE PCI_DEVFN(0, 0)
-
-static unsigned int get_mmio_size(void)
-{
- const struct device *dev;
- const struct northbridge_intel_ironlake_config *cfg = NULL;
-
- dev = pcidev_path_on_root(HOST_BRIDGE);
- if (dev)
- cfg = dev->chip_info;
-
- /* If this is zero, it just means devicetree.cb didn't set it */
- if (!cfg || cfg->pci_mmio_size == 0)
- return DEFAULT_PCI_MMIO_SIZE;
- else
- return cfg->pci_mmio_size;
-}
static void program_total_memory_map(struct raminfo *info)
{
@@ -1323,7 +1306,7 @@ static void program_total_memory_map(struct raminfo *info)
uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
}
- mmio_size = get_mmio_size();
+ mmio_size = DEFAULT_PCI_MMIO_SIZE;
tom = info->total_memory_mb;
if (tom == 4096)