diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/ram_calc.c | 34 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/ram_calc.c | 34 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 34 |
4 files changed, 99 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c22b491c66..780bed48b1 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -18,11 +18,14 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> +#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> #include <cbmem.h> +#include <program_loading.h> #include "gm45.h" /* @@ -92,7 +95,36 @@ void *cbmem_top(void) return (void *) top_of_ram; } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. If you modify this to + * cover TSEG, make sure UMA region is not set with WRBACK as it + * causes hard-to-recover boot failures. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 16ae55f68a..8ebb422551 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -905,7 +905,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index d962cc3daa..a8ef065fb2 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -17,10 +17,13 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <arch/cpu.h> #include <cbmem.h> #include "i945.h" #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> static uintptr_t smm_region_start(void) { @@ -76,7 +79,36 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. If you modify this to + * cover TSEG, make sure UMA region is not set with WRBACK as it + * causes hard-to-recover boot failures. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 2a5d7e5752..410e3b623a 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -20,11 +20,14 @@ #include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> +#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> +#include <program_loading.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -100,7 +103,36 @@ void *cbmem_top(void) return (void *) top_of_ram; } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. If you modify this to + * cover TSEG, make sure UMA region is not set with WRBACK as it + * causes hard-to-recover boot failures. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } |