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-rw-r--r--src/northbridge/intel/e7505/raminit.c15
-rw-r--r--src/northbridge/intel/gm45/memmap.c1
-rw-r--r--src/northbridge/intel/haswell/acpi.c1
-rw-r--r--src/northbridge/intel/haswell/gma.c1
-rw-r--r--src/northbridge/intel/i440bx/memmap.c1
-rw-r--r--src/northbridge/intel/i440bx/raminit.c1
-rw-r--r--src/northbridge/intel/i945/early_init.c1
-rw-r--r--src/northbridge/intel/i945/gma.c1
-rw-r--r--src/northbridge/intel/i945/raminit.c4
-rw-r--r--src/northbridge/intel/i945/rcven.c3
-rw-r--r--src/northbridge/intel/ironlake/northbridge.c1
-rw-r--r--src/northbridge/intel/ironlake/raminit.c2
-rw-r--r--src/northbridge/intel/pineview/memmap.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c6
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c1
-rw-r--r--src/northbridge/intel/x4x/raminit.c2
18 files changed, 0 insertions, 44 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 892bfadd23..444ab162ff 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -340,7 +340,6 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
if (value > 2)
die("Bad SPD value\n");
if (value == 2) {
-
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
if (value < 0)
@@ -413,14 +412,12 @@ static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address)
struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
if (sz.side1 > 0) {
-
value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS);
die_on_spd_error(value);
sz.side1 += value & 0xf;
if (sz.side2 > 0) {
-
// Double-sided DIMM
if (value & 0xF0)
sz.side2 += value >> 4; // Asymmetric
@@ -496,7 +493,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// since we only support dual-channel.
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t channel0_dimm = ctrl->channel0[i];
uint16_t channel1_dimm = ctrl->channel1[i];
uint8_t bDualChannel = 1;
@@ -565,7 +561,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// NOTE: unpopulated DIMMs cause read to fail
spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
-
printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
@@ -580,7 +575,6 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
if (!are_spd_values_equal
(dual_channel_parameters[j], channel0_dimm,
channel1_dimm)) {
-
bDualChannel = 0;
break;
}
@@ -653,7 +647,6 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
* Seems like rows 4-7 overlap with 0-3.
*/
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
-
uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
@@ -800,7 +793,6 @@ static void configure_e7501_ram_addresses(const struct mem_controller
pci_write_config32(MCHDEV, DRB_ROW_4, 0);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t dimm_socket_address = ctrl->channel0[i];
struct dimm_size sz;
@@ -1020,7 +1012,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
uint32_t dimm_compatible_cas_latencies;
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
uint16_t dimm_socket_address;
if (!(dimm_mask & (1 << i)))
@@ -1098,7 +1089,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
dram_timing |= DRT_CAS_2_0;
dram_read_timing |= 0x0222;
} else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
-
uint32_t dram_row_attributes =
pci_read_config32(MCHDEV, DRA);
@@ -1111,7 +1101,6 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
&& (dram_row_attributes & 0xff00)
&& (dram_row_attributes & 0xff0000)
&& (dram_row_attributes & 0xff000000)) {
-
// All slots populated
dram_read_timing |= 0x0882;
} else {
@@ -1179,7 +1168,6 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
*/
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
uint32_t dimm_refresh_mode;
int value;
uint16_t dimm_socket_address;
@@ -1250,7 +1238,6 @@ static void configure_e7501_row_attributes(const struct mem_controller
uint32_t row_attributes = 0;
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint16_t dimm_socket_address = ctrl->channel0[i];
struct dimm_size page_size;
struct dimm_size sdram_width;
@@ -1300,7 +1287,6 @@ static void enable_e7501_clocks(uint8_t dimm_mask)
pci_write_config8(MCHDEV, 0x8e, 0xb0);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
uint8_t socket_mask = 1 << i;
if (dimm_mask & socket_mask)
@@ -1702,7 +1688,6 @@ void sdram_initialize(void)
/* If this is a warm boot, some initialisation can be skipped */
if (!e7505_mch_is_ready()) {
-
/* The real MCH initialisation. */
timestamp_add_now(TS_INITRAM_START);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 35ec41da46..d03639919a 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -127,5 +127,4 @@ void fill_postcar_frame(struct postcar_frame *pcf)
MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
-
}
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 8d179aaa62..f3c107b323 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -36,7 +36,6 @@ static unsigned long acpi_fill_dmar(unsigned long current)
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
-
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 48a0ba54c7..9e9f9804f5 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -124,7 +124,6 @@ u32 gtt_read(u32 reg)
u32 val;
val = read32(res2mmio(gtt_res, reg, 0));
return val;
-
}
void gtt_write(u32 reg, u32 data)
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 5cee1b4d38..204e83badf 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -59,5 +59,4 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
MTRR_TYPE_WRBACK);
-
}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index ec93563699..54c1b363fc 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -755,7 +755,6 @@ static void set_dram_row_attributes(void)
/* This is 440BX! We do EDO too! */
if (value == SPD_MEMORY_TYPE_EDO
|| value == SPD_MEMORY_TYPE_SDRAM) {
-
if (value == SPD_MEMORY_TYPE_EDO) {
edo = 1;
} else if (value == SPD_MEMORY_TYPE_SDRAM) {
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d61949fc42..eea20282cd 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -290,7 +290,6 @@ static void i945_setup_egress_port(void)
printk(BIOS_DEBUG, "timeout!\n");
else
printk(BIOS_DEBUG, "ok\n");
-
}
static void ich7_setup_dmi_rcrb(void)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index d99a733773..5cbd62974d 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -537,7 +537,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
vga_sr_write(1, vga_sr_read(1) & ~0x20);
return 0;
-
}
/* compare the header of the vga edid header */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 2613b81670..a37754b7f3 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -49,7 +49,6 @@ static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
return sysinfo->spd_addresses[device];
else
return 0x50 + device;
-
}
static __attribute__((noinline)) void do_ram_command(u32 command)
@@ -226,7 +225,6 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
/* Write back clears bit 2 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
do_reset = true;
-
}
if (reg8 & (1 << 7)) {
@@ -289,7 +287,6 @@ struct timings {
*/
static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings)
{
-
int i, j;
u8 raw_spd[SPD_SIZE_MAX_DDR2];
u8 dimm_mask = 0;
@@ -2313,7 +2310,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
static void sdram_thermal_management(void)
{
-
mchbar_write8(TCO1, 0);
mchbar_write8(TCO0, 0);
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 7d497e69a2..024a2630eb 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -83,7 +83,6 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
reg32 |= medium;
}
mchbar_write32(RCVENMT, reg32);
-
}
static int normalize(int channel_offset, u8 *mediumcoarse, u8 *fine)
@@ -190,7 +189,6 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
continue;
break;
-
}
printk(BIOS_DEBUG, "Could not find low strobe\n");
@@ -200,7 +198,6 @@ static int find_strobes_low(int channel_offset, u8 *mediumcoarse, u8 *fine,
static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
struct sys_info *sysinfo)
{
-
int counter;
u32 rcvenmt;
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index e6bc3752d5..d8c8799de5 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -168,7 +168,6 @@ static void ironlake_init(void *const chip_info)
const struct device *const d0f0 = pcidev_on_root(0, 0);
if (d0f0)
pci_update_config32(d0f0, DEVEN, deven_mask, 0);
-
}
static struct device_operations mc_ops = {
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index b84461aef8..b2620975a7 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1552,7 +1552,6 @@ static void read_4090(struct raminfo *info)
rank), 9)
+ (i == 1) * 11; // !!!!
}
-
}
static u32 get_etalon2(int flip, u32 addr)
@@ -2759,7 +2758,6 @@ static void do_ram_training(struct raminfo *info)
timings);
totalrank++;
}
-
}
} else {
for (reg_178 = reg178_center - 12;
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 55d704678c..967a59fad0 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -76,7 +76,6 @@ static uintptr_t northbridge_get_tseg_base(void)
uintptr_t cbmem_top_chipset(void)
{
return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
-
}
void smm_region(uintptr_t *start, size_t *size)
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 085292bb22..2b59b9e6af 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -377,7 +377,6 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
/* Before reusing training data, assert that the CPU has not been replaced */
if (ctrl_cached && cpuid != ctrl_cached->cpu) {
-
/* It is not really worrying on a cold boot, but fatal when resuming from S3 */
printk(s3resume ? BIOS_ALERT : BIOS_NOTICE,
"CPUID %x differs from stored CPUID %x, CPU was replaced!\n",
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 3f5e290c57..f896541288 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -64,7 +64,6 @@ void dram_find_common_params(ramctr_timing *ctrl)
valid_dimms = 0;
FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) {
-
const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot];
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3)
continue;
@@ -1138,7 +1137,6 @@ static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, i
int lane, i;
for (rcven_delta = -25; rcven_delta <= 25; rcven_delta++) {
-
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven
= upperA[lane] + rcven_delta + QCLK_PI;
@@ -1358,7 +1356,6 @@ int receive_enable_calibration(ramctr_timing *ctrl)
FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].rcven -= QCLK_PI;
upperA[lane] -= QCLK_PI;
-
}
} else if (some_high) {
ctrl->timings[channel][slotrank].roundtrip_latency++;
@@ -1657,7 +1654,6 @@ static void train_write_flyby(ramctr_timing *ctrl)
fill_pattern1(ctrl, channel);
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
-
/* Reset read and write WDB pointers */
mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001);
@@ -2501,7 +2497,6 @@ int aggressive_write_training(ramctr_timing *ctrl)
upper[channel][slotrank][lane] =
MIN(rn.end - ctrl->tx_dq_offset[i],
upper[channel][slotrank][lane]);
-
}
}
}
@@ -2621,7 +2616,6 @@ void channel_scrub(ramctr_timing *ctrl)
rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits;
for (bank = 0; bank < 8; bank++) {
for (row = 0; row < rowsize; row += 16) {
-
u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD);
const struct iosav_ssq sequence[] = {
/*
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 82e3e82842..cad86ba51e 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -295,7 +295,6 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data)
case 800:
pei_data->max_ddr3_freq = 1600;
break;
-
}
/*
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index fbdc27a7b0..ecae91be08 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -274,7 +274,6 @@ static unsigned int get_mem_min_tck(void)
/* If non-zero, it was set in the devicetree */
if (cfg->max_mem_clock_mhz) {
-
if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index b4366fb005..3149074e19 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -147,7 +147,6 @@ static enum cb_err ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
dram_print_spd_ddr2(&decoded_dimm);
if (!(decoded_dimm.width & (0x08 | 0x10))) {
-
printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
dimm_idx, s->dimms[dimm_idx].width);
return CB_ERR;
@@ -523,7 +522,6 @@ static void find_dimm_config(struct sysinfo *s)
}
printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
}
-
}
static void checkreset_ddr2(int boot_path)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 10:11:02 +0000