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Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3e128cdff3..63108de893 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -85,7 +85,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Perform some early chipset initialization required * before RAM initialization can work */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + sandybridge_early_initialization(); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); s3resume = southbridge_detect_s3_resume(); |