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path: root/src/northbridge/intel/sandybridge/raminit_native.c
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Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_native.c')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 3613c050ab..0d581f5a57 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -577,13 +577,13 @@ static void dram_freq(ramctr_timing *ctrl)
/* Step 2 - Select frequency in the MCU */
reg1 = ctrl->FRQ;
if (ctrl->base_freq == 100)
- reg1 |= 0x100; /* Enable 100Mhz REF clock */
+ reg1 |= (1 << 8); /* Enable 100Mhz REF clock */
- reg1 |= 0x80000000; /* set running bit */
+ reg1 |= (1 << 31); /* set running bit */
MCHBAR32(MC_BIOS_REQ) = reg1;
int i = 0;
printk(BIOS_DEBUG, "PLL busy... ");
- while (reg1 & 0x80000000) {
+ while (reg1 & (1 << 31)) {
udelay(10);
i++;
reg1 = MCHBAR32(MC_BIOS_REQ);