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Diffstat (limited to 'src/northbridge/intel/pineview/bootblock.c')
-rw-r--r--src/northbridge/intel/pineview/bootblock.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 7fb506e751..61bd2eedcd 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -1,14 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <assert.h>
#include <device/pci_ops.h>
+#include <types.h>
#include "pineview.h"
-#define MMCONF_256_BUSSES 16
-#define ENABLE 1
+static uint32_t encode_pciexbar_length(void)
+{
+ switch (CONFIG_MMCONF_BUS_NUMBER) {
+ case 256: return 0 << 1;
+ case 128: return 1 << 1;
+ case 64: return 2 << 1;
+ default: return dead_code_t(uint32_t);
+ }
+}
void bootblock_early_northbridge_init(void)
{
- pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
- CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
+ const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}