diff options
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a5bfe6f6a9..13dce61325 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,6 @@ #include <cbmem.h> #include <romstage_handoff.h> #include <pc80/mc146818rtc.h> -#include <southbridge/intel/common/gpio.h> #include <types.h> #include "i945.h" @@ -156,21 +155,6 @@ static void i945_setup_bars(void) if (i945_silicon_revision() == 0) printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - - i82801gx_setup_bars(); - - setup_pch_gpios(&mainboard_gpio_map); - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ - outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |