aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/i855pm/northbridge.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel/i855pm/northbridge.c')
-rw-r--r--src/northbridge/intel/i855pm/northbridge.c234
1 files changed, 137 insertions, 97 deletions
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index b43a853eee..38a0a4a196 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -1,8 +1,6 @@
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
-#include <mem.h>
-#include <part/sizeram.h>
#include <device/device.h>
#include <device/pci.h>
#include <stdlib.h>
@@ -10,110 +8,152 @@
#include <bitops.h>
#include "chip.h"
-struct mem_range *sizeram(void)
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+static void pci_domain_read_resources(device_t dev)
+{
+ struct resource *resource;
+ unsigned reg;
+
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, 0);
+ resource->base = 0x400;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO;
+ compute_allocate_resource(&dev->link[0], resource,
+ IORESOURCE_IO, IORESOURCE_IO);
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, 1);
+ resource->limit = 0xffffffffULL;
+ resource->flags = IORESOURCE_MEM;
+ compute_allocate_resource(&dev->link[0], resource,
+ IORESOURCE_MEM, IORESOURCE_MEM);
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *resource;
+
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
{
- static struct mem_range mem[4];
- /* the units of tolm are 64 KB */
- /* the units of drb16 are 64 MB */
- uint16_t tolm, remapbase, remaplimit, drb16;
- uint16_t tolm_r, remapbase_r, remaplimit_r;
- uint8_t drb;
- int remap_high;
- device_t dev;
-
- dev = dev_find_slot(0, 0); // d0f0
- if (!dev) {
- printk_err("Cannot find PCI: 0:0\n");
- return 0;
+ struct resource *resource, *last;
+ device_t mc_dev;
+ uint32_t pci_tolm;
+
+ pci_tolm = 0xffffffffUL;
+ last = &dev->resource[dev->resources];
+ for(resource = &dev->resource[0]; resource < last; resource++)
+ {
+ compute_allocate_resource(&dev->link[0], resource,
+ BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
+
+ resource->flags |= IORESOURCE_STORED;
+ report_resource_stored(dev, resource, "");
+
+ if ((resource->flags & IORESOURCE_MEM) &&
+ (pci_tolm > resource->base))
+ {
+ pci_tolm = resource->base;
+ }
}
-
- /* Calculate and report the top of low memory and
- * any remapping.
- */
- /* Test if the remap memory high option is set */
- remap_high = 0;
-// if(get_option(&remap_high, "remap_memory_high")){
-// remap_high = 0;
-// }
- printk_debug("remap_high is %d\n", remap_high);
- /* get out the value of the highest DRB. This tells the end of
- * physical memory. The units are ticks of 64 MB i.e. 1 means
- * 64 MB.
- */
- drb = pci_read_config8(dev, 0x67);
- drb16 = (uint16_t)drb;
- if(remap_high && (drb16 > 0x08)) {
- /* We only come here if we have at least 512MB of memory,
- * so it is safe to hard code tolm.
- * 0x2000 means 512MB
+
+ mc_dev = dev->link[0].children;
+ if (mc_dev) {
+ /* Figure out which areas are/should be occupied by RAM.
+ * This is all computed in kilobytes and converted to/from
+ * the memory controller right at the edges.
+ * Having different variables in different units is
+ * too confusing to get right. Kilobytes are good up to
+ * 4 Terabytes of RAM...
*/
+ uint16_t tolm_r;
+ unsigned long tomk, tolmk;
+ int idx;
- tolm = 0x2000;
- /* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
- if(drb16 > 0x0040) {
- /* There is more than 4GB of memory put
- * the remap window at the end of ram.
+ /* Get the value of the highest DRB. This tells the end of
+ * the physical memory. The units are ticks of 32MB
+ * i.e. 1 means 32MB.
+ */
+ tomk = ((unsigned long)pci_read_config8(mc_dev, 0x63)) << 15;
+ /* Compute the top of Low memory */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory.
*/
- remapbase = drb16;
- remaplimit = remapbase + 0x38;
- }
- else {
- remapbase = 0x0040;
- remaplimit = remapbase + (drb16-8);
- }
- }
- else {
- tolm = (uint16_t)((dev_root.resource[1].base >> 16)&0x0f800);
- if((tolm>>8) >= (drb16<<2)) {
- tolm = (drb16<<10);
- remapbase = 0x3ff;
- remaplimit = 0;
- }
- else {
- remapbase = drb16;
- remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
+ tolmk = tomk;
}
- }
- /* Write the ram configruation registers,
- * preserving the reserved bits.
- */
- tolm_r = pci_read_config16(dev, 0xc4);
- tolm |= (tolm_r & 0x7ff);
- pci_write_config16(dev, 0xc4, tolm);
- remapbase_r = pci_read_config16(dev, 0xc6);
- remapbase |= (remapbase_r & 0xfc00);
- pci_write_config16(dev, 0xc6, remapbase);
- remaplimit_r = pci_read_config16(dev, 0xc8);
- remaplimit |= (remaplimit_r & 0xfc00);
- pci_write_config16(dev, 0xc8, remaplimit);
-
-#if 0
- printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
-#endif
-
- mem[0].basek = 0;
- mem[0].sizek = 640;
- mem[1].basek = 768;
- /* Convert size in 64K bytes to size in K bytes */
- mem[1].sizek = (tolm << 6) - mem[1].basek;
- mem[2].basek = 0;
- mem[2].sizek = 0;
- if ((drb << 16) > (tolm << 6)) {
- /* We don't need to consider the remap window
- * here because we put it immediately after the
- * rest of ram.
- * All we must do is calculate the amount
- * of unused memory and report it at 4GB.
+ /* Write the ram configuration registers,
+ * preserving the reserved bits.
*/
- mem[2].basek = 4096*1024;
- mem[2].sizek = (drb << 16) - (tolm << 6);
+ tolm_r = pci_read_config16(mc_dev, 0xc4);
+ tolm_r = ((tolmk >> 10) << 3) | (tolm_r & 0xf);
+ pci_write_config16(mc_dev, 0xc4, tolm_r);
+
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, tolmk - 768);
}
- mem[3].basek = 0;
- mem[3].sizek = 0;
-
- return mem;
+ assign_resources(&dev->link[0]);
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+ max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+ return max;
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ struct device_path path;
+
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_i855pm_control = {
- .name = "intel i855pm Northbridge",
+ .name = "intel i855pm Northbridge",
+ .enable_dev = enable_dev,
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-21 15:38:03 +0000