diff options
Diffstat (limited to 'src/northbridge/intel/i5000')
| -rw-r--r-- | src/northbridge/intel/i5000/raminit.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/udelay.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index ffc579a32c..3c913cf66c 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> #include <spd.h> #include <types.h> @@ -1560,7 +1561,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) return 1; } - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch(msr.lo & 7) { case 1: diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 6462fe0316..ff2da6f2a9 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include <console/console.h> /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock @@ -35,7 +36,7 @@ void udelay(u32 us) u32 d; /* ticks per us */ u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; |