diff options
Diffstat (limited to 'src/northbridge/intel/i440bx')
| -rw-r--r-- | src/northbridge/intel/i440bx/ram_calc.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index c9bfc2da9f..dc294f14c6 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -17,7 +17,11 @@ #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <commonlib/helpers.h> +#include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> #include "i440bx.h" void *cbmem_top(void) @@ -62,3 +66,33 @@ void *cbmem_top(void) } return (void *)tom; } + +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache CBMEM region as WB. */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +} |