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Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r--src/northbridge/intel/haswell/memmap.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index ac36e25999..02d120b119 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -9,6 +9,7 @@
#include <cpu/x86/smm.h>
#include <device/pci_ops.h>
#include <cbmem.h>
+#include <security/intel/txt/txt_platform.h>
#include <security/intel/txt/txt_register.h>
#include "haswell.h"
@@ -23,6 +24,11 @@ static size_t northbridge_get_tseg_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
+union dpr_register txt_get_chipset_dpr(void)
+{
+ return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) };
+}
+
/*
* Return the topmost memory address below 4 GiB available for general
* use, from software's view of memory. Do not confuse this with TOLUD,
@@ -39,9 +45,7 @@ static uintptr_t top_of_low_usable_memory(void)
*/
uintptr_t tolum = northbridge_get_tseg_base();
- const union dpr_register dpr = {
- .raw = pci_read_config32(HOST_BRIDGE, DPR),
- };
+ const union dpr_register dpr = txt_get_chipset_dpr();
/* Subtract DMA Protected Range size if enabled */
if (dpr.epm)