2 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index 0d09bb40ef..76ceccac6e 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -19,6 +19,7 @@ struct northbridge_intel_gm45_config {
 	 * Maximum PCI mmio size in MiB.
 	 */
 	u16 pci_mmio_size;
+	int slfm;
 };
 
 #endif				/* NORTHBRIDGE_INTEL_GM45_CHIP_H */
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 31e3de46dc..c6fa0e065c 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -7,6 +7,7 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/speedstep.h>
 #include <cpu/intel/smm_reloc.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -257,3 +258,10 @@ struct chip_operations northbridge_intel_gm45_ops = {
 	CHIP_NAME("Intel GM45 Northbridge")
 	.init = gm45_init,
 };
+
+bool northbridge_support_slfm(void)
+{
+	struct device *gmch = __pci_0_00_0;
+	struct northbridge_intel_gm45_config *config = gmch->chip_info;
+	return config->slfm == 1;
+}