diff options
Diffstat (limited to 'src/northbridge/intel/gm45/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/gm45/ram_calc.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 5af3e16037..af1a46dd67 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <program_loading.h> +#include <cpu/intel/smm/gen1/smi.h> #include "gm45.h" /* @@ -83,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc) } } -uintptr_t smm_region_start(void) +u32 northbridge_get_tseg_base(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -106,13 +107,19 @@ uintptr_t smm_region_start(void) return tor; } +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc) << 10; +} + /* Depending of UMA and TSEG configuration, TSEG might start at any * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; } @@ -135,12 +142,14 @@ void platform_enter_postcar(void) /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache a 8 MiB region below the top of ram and 8 MiB above top of + /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); |