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-rw-r--r--src/northbridge/amd/amdht/AsPsNb.c12
-rw-r--r--src/northbridge/amd/amdht/comlib.c4
-rw-r--r--src/northbridge/amd/amdht/h3finit.c22
-rw-r--r--src/northbridge/amd/amdht/h3finit.h4
-rw-r--r--src/northbridge/amd/amdht/h3ncmn.c46
-rw-r--r--src/northbridge/amd/cimx/rd890/late.c2
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c90
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c6
-rw-r--r--src/northbridge/amd/gx2/raminit.c12
-rw-r--r--src/northbridge/amd/lx/northbridge.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c22
-rw-r--r--src/northbridge/amd/pi/00630F01/acpi/northbridge.asl4
-rw-r--r--src/northbridge/amd/pi/00630F01/dimmSpd.c4
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c36
-rw-r--r--src/northbridge/amd/pi/00660F01/acpi/northbridge.asl16
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c23
-rw-r--r--src/northbridge/amd/pi/00730F01/acpi/northbridge.asl10
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c35
18 files changed, 174 insertions, 176 deletions
diff --git a/src/northbridge/amd/amdht/AsPsNb.c b/src/northbridge/amd/amdht/AsPsNb.c
index e34fa4c7a3..2e6c1038e6 100644
--- a/src/northbridge/amd/amdht/AsPsNb.c
+++ b/src/northbridge/amd/amdht/AsPsNb.c
@@ -43,13 +43,13 @@ u8 getMinNbCOF(void)
numOfNode = getNumOfNodeNb();
/* go through each node for the minimum NbCOF (in multiple of CLKIN/2) */
- for (i=0; i < numOfNode; i++)
+ for (i = 0; i < numOfNode; i++)
{
/* stub function for APIC ID virtualization for large MP system later */
deviceId = translateNodeIdToDeviceIdNb(i);
- /* read all P-state spec registers for NbDid=1 */
- for (j=0; j < 5; j++)
+ /* read all P-state spec registers for NbDid = 1 */
+ for (j = 0; j < 5; j++)
{
AmdPCIRead(MAKE_SBDFO(0,0,deviceId,FN_4,PS_SPEC_REG+(j*PCI_REG_LEN)), &dtemp); /*F4x1E0 + j*4 */
/* get NbDid */
@@ -86,13 +86,13 @@ u8 getMinNbCOF(void)
nextNbFid = nextNbFid >> 1; */
}
}
- if ( i == 0)
+ if (i == 0)
nbFid = nextNbFid;
- else if ( nbFid > nextNbFid )
+ else if (nbFid > nextNbFid)
nbFid = nextNbFid;
}
- /* add the base and convert to 100MHz divide by 2 if DID=1 */
+ /* add the base and convert to 100MHz divide by 2 if DID = 1 */
if (nbDid)
nbFid = (u8) (nbFid + 4);
else
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index 64092ffc64..7a15325588 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -120,7 +120,7 @@ void CALLCONV Amdmemcpy(void *pDst, const void *pSrc, u32 length)
ASSERT(pDst != NULL);
ASSERT(pSrc != NULL);
- while (length--){
+ while (length--) {
// *(((u8*)pDst)++) = *(((u8*)pSrc)++);
*((u8*)pDst) = *((u8*)pSrc);
pDst++;
@@ -134,7 +134,7 @@ void CALLCONV Amdmemset(void *pBuf, u8 val, u32 length)
ASSERT(length <= 32768);
ASSERT(pBuf != NULL);
- while (length--){
+ while (length--) {
//*(((u8*)pBuf)++) = val;
*(((u8*)pBuf)) = val;
pBuf++;
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index bfda13d9e7..b4838b44d5 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -671,7 +671,7 @@ static void htDiscoveryFloodFill(sMainData *pDat)
pDat->TotalLinks++;
- if ( !pDat->sysMatrix[currentNode][token] )
+ if (!pDat->sysMatrix[currentNode][token])
{
pDat->sysDegree[currentNode]++;
pDat->sysDegree[token]++;
@@ -745,8 +745,8 @@ static BOOL isoMorph(u8 i, sMainData *pDat)
{
for (k = 0; k < nodecnt; k++)
{
- if ( pDat->sysMatrix[j][k] !=
- pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]] )
+ if (pDat->sysMatrix[j][k] !=
+ pDat->dbMatrix[pDat->Perm[j]][pDat->Perm[k]])
return FALSE;
}
}
@@ -1356,12 +1356,12 @@ static void regangLinks(sMainData *pDat)
pDat->PortList[i].SelRegang = FALSE;
pDat->PortList[i+1].SelRegang = FALSE;
- if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU))
+ if ((pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU))
continue; /* Only process CPU to CPU links */
for (j = i+2; j < pDat->TotalLinks*2; j += 2)
{
- if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) )
+ if ((pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU))
continue; /* Only process CPU to CPU links */
if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID)
@@ -1506,7 +1506,7 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
cbPCBBAUpstreamWidth = 16;
#endif
- if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
+ if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
{
if (pDat->HtBlock->AMD_CB_Cpu2CpuPCBLimits)
{
@@ -1639,7 +1639,7 @@ static void hammerSublinkFixup(sMainData *pDat)
{
if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */
(loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */
- (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */
+ (loFreq != 2)) /* {13, 2} 2400MHz / 400MHz 6:1 */
downgrade = TRUE;
}
else if (hiFreq == 11)
@@ -1651,19 +1651,19 @@ static void hammerSublinkFixup(sMainData *pDat)
{
if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */
(loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */
- (loFreq != 0) ) /* { 9, 0} 1600MHz / 200MHz 8:1 */
+ (loFreq != 0)) /* { 9, 0} 1600MHz / 200MHz 8:1 */
downgrade = TRUE;
}
else if (hiFreq == 7)
{
if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */
- (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */
+ (loFreq != 0)) /* { 7, 0} 1200MHz / 200MHz 6:1 */
downgrade = TRUE;
}
else if (hiFreq == 5)
{
if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */
- (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */
+ (loFreq != 0)) /* { 5, 0} 800MHz / 200MHz 4:1 */
downgrade = TRUE;
}
else if (hiFreq == 2)
@@ -1807,7 +1807,7 @@ static void tuning(sMainData *pDat)
/* For each node, invoke northbridge specific buffer tunings or
* system specific customizations.
*/
- for (i=0; i < pDat->NodesDiscovered + 1; i++)
+ for (i = 0; i < pDat->NodesDiscovered + 1; i++)
{
if ((pDat->HtBlock->AMD_CB_CustomizeBuffers == NULL)
|| !pDat->HtBlock->AMD_CB_CustomizeBuffers(i))
diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h
index ab2dace20c..c9737929a1 100644
--- a/src/northbridge/amd/amdht/h3finit.h
+++ b/src/northbridge/amd/amdht/h3finit.h
@@ -358,7 +358,7 @@ typedef struct {
*
* ---------------------------------------------------------------------------------------
*/
- BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
+ BOOL (*AMD_CB_CustomizeTrafficDistribution)(void);
/**----------------------------------------------------------------------------------------
@@ -379,7 +379,7 @@ typedef struct {
*
* ---------------------------------------------------------------------------------------
*/
- BOOL (*AMD_CB_CustomizeBuffers)( u8 node );
+ BOOL (*AMD_CB_CustomizeBuffers)(u8 node);
/**----------------------------------------------------------------------------------------
*
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
index cbe90e03e2..0d0055b4f6 100644
--- a/src/northbridge/amd/amdht/h3ncmn.c
+++ b/src/northbridge/amd/amdht/h3ncmn.c
@@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb)
* @param[in] link = the link on that Node to examine
* @param[in] *nb = this northbridge
* @return true - The link has the following status
- * linkCon=1, Link is connected
- * InitComplete=1, Link initialization is complete
- * NC=0, Link is coherent
- * UniP-cLDT=0, Link is not Uniprocessor cLDT
- * LinkConPend=0 Link connection is not pending
+ * linkCon = 1, Link is connected
+ * InitComplete = 1, Link initialization is complete
+ * NC = 0, Link is coherent
+ * UniP-cLDT = 0, Link is not Uniprocessor cLDT
+ * LinkConPend = 0 Link connection is not pending
* false- The link has some other status
*
*****************************************************************************/
@@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb)
/* FN0_98/A4/C4 = LDT Type Register */
AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
- /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */
+ /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */
return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT;
#else
return 0;
@@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb)
CPU_NB_FUNC_03,
REG_NB_DOWNCORE_3X190),
3, 0, &leveling);
- for (i=0; i<cores; i++)
+ for (i = 0; i < cores; i++)
{
if (leveling & ((u32) 1 << i))
{
@@ -662,7 +662,7 @@ static u8 fam15GetNumCoresOnNode(u8 node, cNorthBridge *nb)
CPU_NB_FUNC_03,
REG_NB_DOWNCORE_3X190),
31, 0, &leveling);
- for (i=0; i<cores; i++)
+ for (i = 0; i < cores; i++)
{
if (leveling & ((u32) 1 << i))
{
@@ -1122,11 +1122,11 @@ static u8 readSbLink(cNorthBridge *nb)
* @param[in] link = the Link on that node to examine
* @param[in] *nb = this northbridge
* @return = true - The link has the following status
- * LinkCon=1, Link is connected
- * InitComplete=1,Link initilization is complete
- * NC=1, Link is coherent
- * UniP-cLDT=0, Link is not Uniprocessor cLDT
- * LinkConPend=0 Link connection is not pending
+ * LinkCon = 1, Link is connected
+ * InitComplete = 1,Link initilization is complete
+ * NC = 1, Link is coherent
+ * UniP-cLDT = 0, Link is not Uniprocessor cLDT
+ * LinkConPend = 0 Link connection is not pending
* false- The link has some other status
*
* ---------------------------------------------------------------------------------------
@@ -1143,7 +1143,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb)
/* FN0_98/A4/C4 = LDT Type Register */
AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
- /* Verify linkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */
+ /* Verify linkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */
return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT;
}
@@ -1922,7 +1922,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *
CPU_HTNB_FUNC_00,
REG_HT_TRAFFIC_DIST_0X164),
23, 16, &links01);
- /* DstNode = 1, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */
+ /* DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */
temp = 0x0107;
AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(0),
makePCIBusFromNode(0),
@@ -1939,7 +1939,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *
CPU_HTNB_FUNC_00,
REG_HT_TRAFFIC_DIST_0X164),
23, 16, &links10);
- /* DstNode = 0, cHTPrbDistEn=1, cHTRspDistEn=1, cHTReqDistEn=1 */
+ /* DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1 */
temp = 0x0007;
AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(1),
makePCIBusFromNode(1),
@@ -2088,13 +2088,13 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
makePCIDeviceFromNode(node),
CPU_NB_FUNC_03,
REG_NB_FIFOPTR_3XDC);
- for (i=0; i < nb->maxLinks; i++)
+ for (i = 0; i < nb->maxLinks; i++)
{
temp = 0;
if (nb->verifyLinkIsCoherent(node, i, nb))
{
temp = 0x26;
- ASSERT(i<3);
+ ASSERT(i < 3);
AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp);
}
else
@@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
if (nb->verifyLinkIsNonCoherent(node, i, nb))
{
temp = 0x25;
- ASSERT(i<3);
+ ASSERT(i < 3);
AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp);
}
}
@@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
* Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3
* (and, one assumes, from there on).
*/
- for (i=0; i < (pDat->NodesDiscovered +1); i++)
+ for (i = 0; i < (pDat->NodesDiscovered +1); i++)
{
AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i),
makePCIBusFromNode(i),
@@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
}
}
- for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++)
+ for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++)
{
isOuter = FALSE;
/* Check for outer node by scanning the config maps on node 0 for one
@@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
if (node == (u8)temp)
{
/* This is an outer node. Tune it appropriately. */
- for (j=0; j < nb->maxLinks; j++)
+ for (j = 0; j < nb->maxLinks; j++)
{
if (isErrata153)
{
@@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb)
if (isErrata153)
{
/* Tuning for inner node coherent links */
- for (j=0; j < nb->maxLinks; j++)
+ for (j = 0; j < nb->maxLinks; j++)
{
if (nb->verifyLinkIsCoherent(node, j, nb))
{
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index c10428dd33..9581527a44 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -78,7 +78,7 @@ static void rd890_enable(device_t dev)
0, (devfn >> 3), (devfn & 0x07), dev->enabled);
/* we only do this once */
- if (devfn==0) {
+ if (devfn == 0) {
/* CIMX configuration defualt initialize */
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
if (gConfig.StandardHeader.CalloutPtr != NULL) {
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index f21d717a55..3b020165b3 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -35,24 +35,24 @@ struct gliutable
};
struct gliutable gliu0table[] = {
- {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
- {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
- {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
- {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+ {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
+ {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
+ {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+ {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
+ {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable gliu1table[] = {
- {.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
- {.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
- {.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
- {.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
- {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+ {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
+ {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
+ {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
+ {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+ {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
+ {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
@@ -64,51 +64,51 @@ struct msrinit
};
struct msrinit ClockGatingDefault[] = {
- {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
+ {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
- {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
- {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
- {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
- {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
+ {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
+ {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
+ {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
+ {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
+ {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* All On */
struct msrinit ClockGatingAllOn[] = {
- {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}},
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
+ {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}},
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* Performance */
struct msrinit ClockGatingPerformance[] = {
- {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
+ {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* SET GeodeLink PRIORITY */
struct msrinit GeodeLinkPriorityTable[] = {
- {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
- {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
- {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */
- {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */
- {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */
- {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */
- {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */
+ {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */
+ {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */
+ {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */
+ {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */
+ {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */
+ {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */
+ {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
};
@@ -422,7 +422,7 @@ static uint64_t getShadow(void)
msr_t msr = { 0, 0 };
msr = rdmsr(GLIU0_P2D_SC_0);
- return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
+ return (((uint64_t) msr.hi) << 32) | msr.lo;
}
/* Set the cache RConf registers for the memory hole.
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 303d64a108..0bae76dda0 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -88,7 +88,7 @@ static void pll_reset(void)
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* If the "we've already been here" flag is set, don't reconfigure the pll */
- if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
+ if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED))
{ /* we haven't configured the PLL; do it now */
/* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
@@ -145,8 +145,8 @@ static void pll_reset(void)
/* CheckPCIsync: */
/* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
/* look up the real divider... if we get a 0 we have serious problems */
- if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
- (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
+ if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
+ (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)))
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index db10138b34..6e66d7dcf5 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -97,7 +97,7 @@ static void auto_size_dimm(unsigned int dimm)
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
printk(BIOS_DEBUG, "BEFORT CTZ\n");
dimm_size = __builtin_ctz(dimm_size);
- printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");
+ printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n");
if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
@@ -130,7 +130,7 @@ static void auto_size_dimm(unsigned int dimm)
* Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
* so lower 3 address bits are dont_cares. So from the table above,
* it's easier to see what the old code is doing: if for example,
- * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
+ * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K.
*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
@@ -142,10 +142,10 @@ static void auto_size_dimm(unsigned int dimm)
}
printk(BIOS_DEBUG, ">11address test\n");
spd_byte -= 7;
- if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */
- spd_byte = 7; /* which means >16k so set to disabled */
+ if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */
+ spd_byte = 7; /* which means > 16k so set to disabled */
}
- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */
printk(BIOS_DEBUG, "RDMSR CF07\n");
msr = rdmsr(MC_CF07_DATA);
@@ -230,7 +230,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
static u8 getcasmap(u32 dimm, u16 glspeed)
{
u16 dimm_speed;
- u8 spd_byte, casmap, casmap_shift=0;
+ u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/
casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 2ba4a0415d..a40a628187 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -91,7 +91,7 @@ struct msr_defaults {
/* 180d is left at default, e0000-fffff is non-cached */
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
/* we will not set 0x180f, the DMM,yet */
- //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+ //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index c540f9a399..395d9253a9 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -106,7 +106,7 @@ static void auto_size_dimm(unsigned int dimm)
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
banner("BEFORT CTZ");
dimm_size = __builtin_ctz(dimm_size);
- banner("TEST DIMM SIZE>8");
+ banner("TEST DIMM SIZE > 8");
if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
@@ -131,12 +131,12 @@ static void auto_size_dimm(unsigned int dimm)
*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
*;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)
-*; *AP=autoprecharge bit
+*; *AP = autoprecharge bit
*
*;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
*;so lower 3 address bits are dont_cares.So from the table above,
-*;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
-*;it adds 3 to get 10, then does 2^10=1K. Get it?*/
+*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h),
+*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
banner("MAXCOLADDR");
@@ -147,10 +147,10 @@ static void auto_size_dimm(unsigned int dimm)
}
banner(">12address test");
spd_byte -= 7;
- if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
- spd_byte = 7; /* which means >32k so set to disabled */
+ if (spd_byte > 5) { /* if the value is above 6 it means > 12 address lines */
+ spd_byte = 7; /* which means > 32k so set to disabled */
}
- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */
banner("RDMSR CF07");
msr = rdmsr(MC_CF07_DATA);
@@ -182,7 +182,7 @@ static void checkDDRMax(void)
}
/* I don't think you need this check.
- if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
+ if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) {
printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
@@ -242,7 +242,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3,
static u8 getcasmap(u32 dimm, u16 glspeed)
{
u16 dimm_speed;
- u8 spd_byte, casmap, casmap_shift=0;
+ u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/
casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
@@ -730,8 +730,8 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
}
/* Set PMode0 Sensitivity Counter */
- msr.lo = 0; /* pmode 0=0 most aggressive */
- msr.hi = 0x200; /* pmode 1=200h */
+ msr.lo = 0; /* pmode 0 = 0 most aggressive */
+ msr.hi = 0x200; /* pmode 1 = 200h */
wrmsr(MC_CF_PMCTR, msr);
/* Set PMode1 Up delay enable */
diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
index 689203a9e4..c2b3aac4c5 100644
--- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR2) {
Name(_ADR, 0x00020000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS2) } /* APIC mode */
+ If(PMOD) { Return(APS2) } /* APIC mode */
Return (PS2) /* PIC Mode */
} /* end _PRT */
} /* end PBR2 */
@@ -60,7 +60,7 @@ Device(PBR3) {
Name(_ADR, 0x00030000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS3) } /* APIC mode */
+ If(PMOD) { Return(APS3) } /* APIC mode */
Return (PS3) /* PIC Mode */
} /* end _PRT */
} /* end PBR3 */
diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c
index 889db62a4d..50eee51864 100644
--- a/src/northbridge/amd/pi/00630F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c
@@ -35,9 +35,9 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
if ((dev == 0) || (config == 0))
return AGESA_ERROR;
- if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
+ if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
return AGESA_ERROR;
- if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
+ if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
return AGESA_ERROR;
if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 0f9e5f5366..8a40280938 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -88,10 +88,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
- for (i=0; i<node_nums; i++)
+ tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -101,10 +101,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -131,7 +131,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -160,7 +160,7 @@ static u32 amdfam15_nodeid(device_t dev)
unsigned busn;
busn = dev->bus->secondary;
- if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)){
+ if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
@@ -403,8 +403,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate ))
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
break;
}
else
@@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev)
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
device_t reg_dev;
- if (reg<0xc0) { // mmio
+ if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30);
@@ -687,7 +687,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id == -1) {
resource_t limitk_pri = 0;
- for (i=0; i<node_nums; i++) {
+ for (i = 0; i < node_nums; i++) {
dram_base_mask_t d;
resource_t base_k, limit_k;
d = get_dram_base_mask(i);
@@ -811,11 +811,11 @@ static void domain_set_resources(device_t dev)
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -981,7 +981,7 @@ static void cpu_bus_scan(device_t dev)
}
sysconf_init(dev_mc);
#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
if (pci_domain->link_list && !pci_domain->link_list->next) {
struct bus *new_link = new_link(pci_domain);
pci_domain->link_list->next = new_link;
@@ -1059,10 +1059,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0; //default one core
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1081,10 +1081,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
index cde5182123..022b347d29 100644
--- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
+ If(PMOD) { Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
@@ -60,7 +60,7 @@ Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
+ If(PMOD) { Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
@@ -70,7 +70,7 @@ Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
+ If(PMOD) { Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
@@ -80,7 +80,7 @@ Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
+ If(PMOD) { Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
@@ -90,7 +90,7 @@ Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS8) } /* APIC mode */
+ If(PMOD) { Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -105,7 +105,7 @@ Device(PBRA) {
Name(_ADR, 0x00030003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSA) } /* APIC mode */
+ If(PMOD) { Return(APSA) } /* APIC mode */
Return (PSA) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -115,7 +115,7 @@ Device(PBRB) {
Name(_ADR, 0x00030004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSB) } /* APIC mode */
+ If(PMOD) { Return(APSB) } /* APIC mode */
Return (PSB) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
@@ -125,7 +125,7 @@ Device(PBRC) {
Name(_ADR, 0x00030005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APSC) } /* APIC mode */
+ If(PMOD) { Return(APSC) } /* APIC mode */
Return (PSC) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index efee0a4f05..1ca0df98e4 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -100,10 +100,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -134,7 +134,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -396,9 +396,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
- )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
#endif
break;
}
@@ -817,11 +816,11 @@ static void domain_set_resources(device_t dev)
}
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -1059,10 +1058,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0;
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1081,10 +1080,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
index 4e6d13e74e..f74b31a080 100644
--- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
@@ -50,7 +50,7 @@ Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
+ If(PMOD) { Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
@@ -60,7 +60,7 @@ Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
+ If(PMOD) { Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
@@ -70,7 +70,7 @@ Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
+ If(PMOD) { Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
@@ -80,7 +80,7 @@ Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
+ If(PMOD) { Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
@@ -90,7 +90,7 @@ Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS8) } /* APIC mode */
+ If(PMOD) { Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 6d5418a532..b778da5903 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -83,9 +83,9 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
+ tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
#if 0
// FIXME: can we use VGA reg instead?
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
@@ -97,7 +97,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
tempreg |= PCI_IO_BASE_NO_ISA;
}
#endif
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -107,10 +107,10 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg;
/* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
- for (i=0; i<nodes; i++)
+ for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
- for (i=0; i<node_nums; i++)
+ for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg);
}
@@ -141,7 +141,7 @@ static void get_fx_devs(void)
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
die("Cannot find 0:0x18.[0|1]\n");
}
- printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs);
}
static u32 f1_read_config32(unsigned reg)
@@ -417,9 +417,8 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
- )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate))
#endif
break;
}
@@ -646,7 +645,7 @@ static void domain_read_resources(device_t dev)
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
device_t reg_dev;
- if (reg<0xc0) { // mmio
+ if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30);
@@ -709,7 +708,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id == -1) {
resource_t limitk_pri = 0;
- for (i=0; i<node_nums; i++) {
+ for (i = 0; i < node_nums; i++) {
dram_base_mask_t d;
resource_t base_k, limit_k;
d = get_dram_base_mask(i);
@@ -841,11 +840,11 @@ static void domain_set_resources(device_t dev)
//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
/* split the region to accommodate pci memory space */
- if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -1011,7 +1010,7 @@ static void cpu_bus_scan(device_t dev)
}
sysconf_init(dev_mc);
#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
- if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+ if (node_nums > 32) { // need to put node 32 to node 63 to bus 0xfe
if (pci_domain->link_list && !pci_domain->link_list->next) {
struct bus *new_link = new_link(pci_domain);
pci_domain->link_list->next = new_link;
@@ -1090,10 +1089,10 @@ static void cpu_bus_scan(device_t dev)
siblings = 0; //default one core
}
int enable_node = cdb_dev && cdb_dev->enabled;
- printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+ printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
- for (j = 0; j <= siblings; j++ ) {
+ for (j = 0; j <= siblings; j++) {
u32 lapicid_start = 0;
/*
@@ -1112,10 +1111,10 @@ static void cpu_bus_scan(device_t dev)
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
- printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+ printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
- printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+ printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n",
i, j, apic_id);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 01:24:53 +0000