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-rw-r--r--src/northbridge/amd/amdmct/amddefs.h66
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c57
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c8
3 files changed, 76 insertions, 55 deletions
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 42ad32b1e2..d2dfbccfe9 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -49,32 +49,34 @@
/*
* Groups - Create as many as you wish, from the above public values
*/
-#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K)
-#define AMD_NPT_F3 (AMD_NPT_F3L)
-#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3)
-#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B)
-#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx)
-#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2)
-#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0)
-#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
-#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
-#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
-#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
-#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0))
-#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
-#define AMD_DR_ALL (AMD_DR_Bx)
-#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
-#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
-#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
-#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
-#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
-#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
-#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
-#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1)
-#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
-#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
+#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K)
+#define AMD_NPT_F3 (AMD_NPT_F3L)
+#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3)
+#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B)
+#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx)
+#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2)
+#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0)
+#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
+#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
+#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
+#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1)
+#define AMD_DR_Ex (AMD_PH_E0)
+#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
+#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
+#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0))
+#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
+#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)
+#define AMD_DR_ALL (AMD_DR_Bx)
+#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
+#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
+#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
+#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
+#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
+#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
+#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
+#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
-#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0)
+#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0)
/*
* Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE
@@ -87,9 +89,9 @@
#define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */
#define AMD_PTYPE_UMA 0x040 /* UMA required */
- /*
- * Groups - Create as many as you wish, from the above public values
- */
+/*
+ * Groups - Create as many as you wish, from the above public values
+ */
#define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */
@@ -98,11 +100,11 @@
*/
#define HTPHY_LINKTYPE_HT3 0x00000001
#define HTPHY_LINKTYPE_HT1 0x00000002
-#define HTPHY_LINKTYPE_COHERENT 0x00000004
+#define HTPHY_LINKTYPE_COHERENT 0x00000004
#define HTPHY_LINKTYPE_NONCOHERENT 0x00000008
#define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT)
#define HTPHY_LINKTYPE_GANGED 0x00000010
-#define HTPHY_LINKTYPE_UNGANGED 0x00000020
+#define HTPHY_LINKTYPE_UNGANGED 0x00000020
#define HTPHY_LINKTYPE_ALL 0x7FFFFFFF
@@ -110,7 +112,7 @@
* CPU HT PHY REGISTERS, FIELDS, AND MASKS
*/
#define HTPHY_OFFSET_MASK 0xE00001FF
-#define HTPHY_WRITE_CMD 0x40000000
+#define HTPHY_WRITE_CMD 0x40000000
#define HTPHY_IS_COMPLETE_MASK 0x80000000
#define HTPHY_DIRECT_MAP 0x20000000
#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF
@@ -158,4 +160,4 @@
#define AMD_PKGTYPE_S1gX 2
#define AMD_PKGTYPE_G34 3
#define AMD_PKGTYPE_ASB2 4
-#define AMD_PKGTYPE_C32 5
+#define AMD_PKGTYPE_C32 5 \ No newline at end of file
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 27fa7ae018..1d48070084 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1203,6 +1203,7 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
int8_t max_range;
uint8_t max_node;
uint64_t max_range_limit;
+ uint8_t byte;
uint32_t dword;
uint32_t dword2;
uint64_t qword;
@@ -1222,7 +1223,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8));
dword2 = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8));
- qword = ((((uint64_t)dword) >> 16) & 0xffff) << 24;
+ qword = 0xffffff;
+ qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24;
qword |= (((uint64_t)dword2) & 0xff) << 40;
if (qword > max_range_limit) {
@@ -1232,26 +1234,35 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat,
}
}
- if (pDCTstat->Node_ID == max_node) {
- if (max_range >= 0) {
- if (interleaved)
- /* Move upper limit down by 16M * the number of nodes */
- max_range_limit -= (0x1000000 * num_nodes);
- else
- /* Move upper limit down by 16M */
- max_range_limit -= 0x1000000;
-
- /* Store modified range */
- dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8));
- dword &= ~(0xffff << 16); /* DramLimit[39:24] = max_range_limit[39:24] */
- dword |= (max_range_limit >> 24) & 0xffff;
- Set_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8), dword);
-
- dword = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8));
- dword &= ~(0xffff << 16); /* DramLimit[47:40] = max_range_limit[47:40] */
- dword |= (max_range_limit >> 40) & 0xff;
- Set_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8), dword);
- }
+ if (max_range >= 0) {
+ if (interleaved)
+ /* Move upper limit down by 16M * the number of nodes */
+ max_range_limit -= (0x1000000 * num_nodes);
+ else
+ /* Move upper limit down by 16M */
+ max_range_limit -= 0x1000000;
+
+ /* Disable the range */
+ dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8));
+ byte = dword & 0x3;
+ dword &= ~(0x3);
+ Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword);
+
+ /* Store modified range */
+ dword = Get_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8));
+ dword &= ~(0xffff << 16); /* DramLimit[39:24] = max_range_limit[39:24] */
+ dword |= ((max_range_limit >> 24) & 0xffff) << 16;
+ Set_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8), dword);
+
+ dword = Get_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8));
+ dword &= ~0xff; /* DramLimit[47:40] = max_range_limit[47:40] */
+ dword |= (max_range_limit >> 40) & 0xff;
+ Set_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8), dword);
+
+ /* Reenable the range */
+ dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8));
+ dword |= byte;
+ Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword);
}
/* Determine save state destination node */
@@ -1538,8 +1549,8 @@ restartinit:
pDCTstat = pDCTstatA + Node;
if (pDCTstat->NodePresent) {
- lock_dram_config(pMCTstat, pDCTstat);
set_cc6_save_enable(pMCTstat, pDCTstat, 1);
+ lock_dram_config(pMCTstat, pDCTstat);
}
}
}
@@ -5118,7 +5129,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
/* get base/limit from Node0 */
reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */
val = Get_NB32(dev, reg);
- Drambase = val >> ( 16 + 3);
+ Drambase = val >> (16 + 3);
reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */
val = Get_NB32(dev, reg);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 0a51b1a228..6ab33a3b1e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -155,6 +155,14 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
if (MemClrECC) {
MCTMemClrSync_D(pMCTstat, pDCTstatA);
}
+
+ if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
+ /* Set up message triggered C1E */
+ val = pci_read_config32(pDCTstat->dev_nbmisc, 0xd4);
+ val &= ~(0x1 << 15); /* StutterScrubEn = DRAM scrub enabled */
+ val |= (mctGet_NVbits(NV_DramBKScrub)?1:0) << 15;
+ pci_write_config32(pDCTstat->dev_nbmisc, 0xd4, val);
+ }
} /* if Node present */
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-20 06:06:11 +0000