diff options
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index db930eff9f..c853b88ff6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -332,7 +332,6 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ continue; - pDCTstat->DqsRdWrPos_Saved = 0; for ( DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { pDCTstat->DQSDelay = DQSWrDelay; @@ -1174,12 +1173,12 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; - if (!pDCTstat->GangedMode) { /* FIXME: not used. */ + if (!pDCTstat->GangedMode) { reg_off = 0x100 * Channel; } /* get the local base addr of the chipselect */ - reg = 0x40 + (receiver << 2); + reg = 0x40 + (receiver << 2) + reg_off; val = Get_NB32(dev, reg); val &= ~0x0F; |