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path: root/src/northbridge/amd/amdmct/mct/mctcsi_d.c
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Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctcsi_d.c')
-rw-r--r--src/northbridge/amd/amdmct/mct/mctcsi_d.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
index e8d26da45f..4841b73bb0 100644
--- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
@@ -45,11 +45,11 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
ChipSel = 0; /* Find out if current configuration is capable */
while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) {
- reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */
+ reg = 0x40+(ChipSel << 2) + reg_off; /* Dram CS Base 0 */
val = Get_NB32(dev, reg);
- if ( val & (1<<CSEnable)) {
+ if (val & (1 << CSEnable)) {
EnChipSels++;
- reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */
+ reg = 0x60+((ChipSel >> 1) << 2)+reg_off; /*Dram CS Mask 0 */
val = Get_NB32(dev, reg);
val >>= 19;
val &= 0x3ff;
@@ -62,7 +62,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
break;
reg = 0x80 + reg_off; /*Dram Bank Addressing */
val = Get_NB32(dev, reg);
- val >>= (ChipSel>>1)<<2;
+ val >>= (ChipSel >> 1) << 2;
val &= 0x0f;
if (EnChipSels == 1)
BankEncd = val;
@@ -80,14 +80,14 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
if (DoIntlv) {
if (!_CsIntCap) {
- pDCTstat->ErrStatus |= 1<<SB_BkIntDis;
+ pDCTstat->ErrStatus |= 1 << SB_BkIntDis;
DoIntlv = 0;
}
}
if (DoIntlv) {
val = Tab_int_D[BankEncd];
- if (pDCTstat->Status & (1<<SB_128bitmode))
+ if (pDCTstat->Status & (1 << SB_128bitmode))
val++;
AddrLoMask = (EnChipSels - 1) << val;
@@ -100,7 +100,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask);
for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) {
- reg = 0x40+(ChipSel<<2) + reg_off; /*Dram CS Base 0 */
+ reg = 0x40+(ChipSel << 2) + reg_off; /*Dram CS Base 0 */
val = Get_NB32(dev, reg);
if (val & 3) {
val_lo = val & AddrLoMask;
@@ -116,7 +116,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
if (ChipSel & 1)
continue;
- reg = 0x60 + ((ChipSel>>1)<<2) + reg_off; /*Dram CS Mask 0 */
+ reg = 0x60 + ((ChipSel >> 1) << 2) + reg_off; /*Dram CS Mask 0 */
val = Get_NB32(dev, reg);
val_lo = val & AddrLoMask;
val_hi = val & AddrHiMask;