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Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r--src/northbridge/amd/amdfam10/amdfam10.h7
-rw-r--r--src/northbridge/amd/amdfam10/debug.c26
-rw-r--r--src/northbridge/amd/amdfam10/raminit_amdmct.c6
-rw-r--r--src/northbridge/amd/amdfam10/setup_resource_map.c20
4 files changed, 27 insertions, 32 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index d292306586..ab4b42e868 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1147,11 +1147,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
@@ -1164,11 +1160,10 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
soft_reset();
#else
- printk(BIOS_DEBUG, "mem trained failed\n");
hard_reset();
#endif
}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7d00af721e..d1fdaf832c 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -108,7 +108,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
val >>= 8;
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static void dump_pci_device(u32 dev)
@@ -122,7 +122,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
int i;
int end = start + size;
print_debug_pci_dev(dev);
- print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+ printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
for(i = start; i < end; i++) {
u32 val;
@@ -135,7 +135,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
@@ -151,7 +151,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
int i;
print_debug_pci_dev(dev);
- print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
+ printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type);
type<<=28;
@@ -163,7 +163,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
val = pci_read_config32_index(dev, index_reg, i|type);
printk(BIOS_DEBUG, " %08x", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -221,7 +221,7 @@ static inline void dump_pci_devices_on_bus(u32 busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
u32 device;
device = ctrl->spd_addr[i];
@@ -241,7 +241,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->spd_addr[i+DIMM_SOCKETS];
if (device) {
@@ -260,14 +260,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static void dump_smbus_registers(void)
{
u32 device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -285,7 +285,7 @@ static void dump_smbus_registers(void)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
@@ -303,7 +303,7 @@ static inline void dump_io_resources(u32 port)
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -312,12 +312,12 @@ static inline void dump_io_resources(u32 port)
static inline void dump_mem(u32 start, u32 end)
{
u32 i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index e5c18a8f45..6b022094d3 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -219,7 +219,7 @@ u32 mctGetLogicalCPUID(u32 Node)
break;
default:
/* FIXME: mabe we should die() here. */
- print_err("FIXME! CPU Version unknown or not supported! \n");
+ printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! \n");
ret = 0;
}
@@ -237,9 +237,9 @@ static void raminit_amdmct(struct sys_info *sysinfo)
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
- print_debug("raminit_amdmct begin:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct begin:\n");
mctAutoInitMCT_D(pMCTstat, pDCTstatA);
- print_debug("raminit_amdmct end:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 2eeca44bf7..ca7f96433c 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -23,7 +23,7 @@
static void setup_resource_map(const u32 *register_values, u32 max)
{
u32 i;
-// print_debug("setting up resource map....");
+// printk(BIOS_DEBUG, "setting up resource map....");
for(i = 0; i < max; i += 3) {
device_t dev;
@@ -37,14 +37,14 @@ static void setup_resource_map(const u32 *register_values, u32 max)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
u32 i;
-// print_debug("setting up resource map offset....");
+// printk(BIOS_DEBUG, "setting up resource map offset....");
for(i = 0; i < max; i += 3) {
device_t dev;
u32 where;
@@ -56,7 +56,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
#define RES_PCI_IO 0x10
@@ -69,12 +69,12 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -127,7 +127,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
@@ -136,11 +136,11 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -189,7 +189,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-19 23:19:44 +0000