summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/agesa/family15
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/amd/agesa/family15')
-rw-r--r--src/northbridge/amd/agesa/family15/dimmSpd.c134
-rw-r--r--src/northbridge/amd/agesa/family15/dimmSpd.h97
-rw-r--r--src/northbridge/amd/agesa/family15/fam15_callouts.c1
3 files changed, 7 insertions, 225 deletions
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c
index 294454c387..375a968dac 100644
--- a/src/northbridge/amd/agesa/family15/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15/dimmSpd.c
@@ -25,143 +25,20 @@
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
-#include "dimmSpd.h"
#include "chip.h"
+#include <northbridge/amd/agesa/dimmSpd.h>
+
/* uncomment for source level debug - GDB gets really confused otherwise. */
//#pragma optimize ("", off)
/**
- * Read a single SPD byte. If the first byte is being read, set up the
- * address and offset. Following bytes auto increment.
- */
-static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
- int offset, int initial_offset)
-{
- unsigned int status = -1;
- UINT64 time_limit;
-
- /* clear status register */
- __outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
- __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
-
- if (offset == initial_offset) {
- /* Set offset, set slave address and start reading */
- __outbyte(iobase + SMBUS_CONTROL_REG, offset);
- __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
- } else {
- /* Issue read command - auto increments to next byte */
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
- }
- /* time limit to avoid hanging for unexpected error status */
- time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
- while (__rdtsc() <= time_limit) {
- status = __inbyte(iobase + SMBUS_STATUS_REG);
- if ((status & SMBUS_INTERRUPT_MASK) == 0)
- continue; /* SMBusInterrupt not set, keep waiting */
- if ((status & HOSTBUSY_MASK) != 0)
- continue; /* HostBusy set, keep waiting */
- break;
- }
-
- if (status != STATUS__COMPLETED_SUCCESSFULLY)
- return AGESA_ERROR;
-
- buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
- return AGESA_SUCCESS;
-}
-
-/**
- * Write a single smbus byte.
- */
-UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer,
- int offset)
-{
- unsigned int status = -1;
- UINT64 time_limit;
-
- /* clear status register */
- __outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
- __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
-
- /* set offset, set slave address, set data and start writing */
- __outbyte(iobase + SMBUS_CONTROL_REG, offset);
- __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT));
- __outbyte(iobase + SMBUS_DATA0_REG, buffer);
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND);
-
- /* time limit to avoid hanging for unexpected error status */
- time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
- while (__rdtsc() <= time_limit) {
- status = __inbyte(iobase + SMBUS_STATUS_REG);
- if ((status & SMBUS_INTERRUPT_MASK) == 0)
- continue; /* SMBusInterrupt not set, keep waiting */
- if ((status & HOSTBUSY_MASK) != 0)
- continue; /* HostBusy set, keep waiting */
- break;
- }
-
- if (status != STATUS__COMPLETED_SUCCESSFULLY)
- return AGESA_ERROR;
-
- return AGESA_SUCCESS;
-}
-
-static void setupFch(UINT16 ioBase)
-{
- AMD_CONFIG_PARAMS StdHeader;
- UINT32 PciData32;
- UINT8 PciData8;
- PCI_ADDR PciAddress;
-
- /* Set SMBus MMIO. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
- PciData32 = (ioBase & 0xFFFFFFF0) | BIT0;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
-
- /* Enable SMBus MMIO. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
- LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
- PciData8 |= BIT0;
- LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
-
- /* Set SMBus clock to 400 KHz */
- __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
-}
-
-/**
- * Read one or more SPD bytes from a DIMM.
- * Start with offset zero and read sequentially.
- * Reads 128 bytes in 7-8 ms at 400 KHz.
- */
-static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
- UINT16 count)
-{
- UINT16 index;
- UINT8 status;
- UINT8 initial_offset = 0;
-
- setupFch(iobase);
-
- for (index = initial_offset; index < count; index++) {
- status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
- initial_offset);
- if (status != AGESA_SUCCESS)
- return status;
- }
-
- return status;
-}
-
-/**
* Gets the SMBus address for an SPD from the array in devicetree.cb
* then read the SPD into the supplied buffer.
*/
-AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr)
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{
UINT8 spdAddress;
- AGESA_READ_SPD_PARAMS *info = infoptr;
ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = NULL;
@@ -182,5 +59,8 @@ AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr)
if (spdAddress == 0)
return AGESA_ERROR;
- return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 256);
+ int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 256);
+ if (err)
+ return AGESA_ERROR;
+ return AGESA_SUCCESS;
}
diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h
deleted file mode 100644
index 167b4a1034..0000000000
--- a/src/northbridge/amd/agesa/family15/dimmSpd.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#ifndef _DIMMSPD_H_
-#define _DIMMSPD_H_
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define READ_BIT 0x01
-
-#define SMBUS_INTERRUPT_MASK 0x02
-#define HOSTBUSY_MASK 0x01
-
-#define SMBUS_READ_BYTE_COMMAND 0x48
-#define SMBUS_READ_COMMAND 0x44
-
-#define SMBUS_WRITE_BYTE_COMMAND 0x48
-
-#define MAX_READ_TSC_COUNT (2000000000 / 10)
-
-#define PMIO_INDEX_REG 0xCD6
-#define PMIO_DATA_REG 0xCD7
-
-#define SMBUS_BAR_LOW_BYTE 0x2C
-#define SMBUS_BAR_HIGH_BYTE 0x2D
-
-#define SMBUS_STATUS_REG 0x00
-#define SMBUS_SLAVE_STATUS_REG 0x01
-#define SMBUS_COMMAND_REG 0x02
-#define SMBUS_CONTROL_REG 0x03
-#define SMBUS_HOST_CMD_REG 0x04
-#define SMBUS_DATA0_REG 0x05
-#define SMBUS_CLOCK_REG 0x0E
-
-#define STATUS__COMPLETED_SUCCESSFULLY 0x02
-
-#define SMBUS_FREQUENCY_CONST 66000000 / 4
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData);
-
-/*
- * This function prototype is only used by the AMD Dinar mainboard. The SMBus
- * write is used to select which socket's SPD will be read by the subsequent
- * SPD read call. This function is being placed in the F15 wrapper code with
- * the other SPD read functions because the next step of the SPD read clean-up
- * will be to move the SMBus read/write functions into the southbridge to make
- * them more generic. Having the writeSmbusByte() function in the same file as
- * the readSmbusByte() function will ensure that the writeSmbusByte() function
- * is not overlooked.
- */
-UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset);
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-#endif
diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.c b/src/northbridge/amd/agesa/family15/fam15_callouts.c
index 3b6549224b..a049a0e6dc 100644
--- a/src/northbridge/amd/agesa/family15/fam15_callouts.c
+++ b/src/northbridge/amd/agesa/family15/fam15_callouts.c
@@ -23,5 +23,4 @@
#include "Ids.h"
#include "OptionsIds.h"
#include "heapManager.h"
-#include <northbridge/amd/agesa/family15/dimmSpd.h>
#include <arch/io.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 13:56:45 +0000