summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/adlrvp/include/baseboard/variants.h2
-rw-r--r--src/mainboard/intel/adlrvp/memory.c58
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c1
-rw-r--r--src/mainboard/intel/adlrvp/spd/Makefile.inc16
-rw-r--r--src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex32
5 files changed, 101 insertions, 8 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 295e1b1e3b..8ecfa77b94 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -20,6 +20,8 @@ enum adl_boardid {
/* ADL-P DDR4 RVPs */
ADL_P_DDR4_1 = 0x14,
ADL_P_DDR4_2 = 0x3F,
+ /* ADL-M LP4 and LP5 RVPs */
+ ADL_M_LP4 = 0x1,
};
/* The next set of functions return the gpio table and fill in the number of
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 85d174363e..f2c378f828 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -161,6 +161,62 @@ static const struct mb_cfg ddr5_mem_config = {
}
};
+static const struct mb_cfg adlm_lp4_mem_config = {
+ .type = MEM_TYPE_LP4X,
+
+ /* DQ byte map */
+ .lpx_dq_map = {
+ .ddr0 = {
+ .dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
+ .dq1 = { 3, 2, 7, 6, 0, 1, 5, 4, }, /* DDR0_DQ1[7:0] */
+ },
+ .ddr1 = {
+ .dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, }, /* DDR1_DQ0[7:0] */
+ .dq1 = { 0, 1, 7, 6, 2, 5, 4, 3, }, /* DDR1_DQ1[7:0] */
+ },
+ .ddr2 = {
+ .dq0 = { 6, 7, 3, 2, 0, 4, 1, 5, }, /* DDR2_DQ0[7:0] */
+ .dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
+ },
+ .ddr3 = {
+ .dq0 = { 2, 6, 7, 3, 1, 5, 0, 4, }, /* DDR3_DQ0[7:0] */
+ .dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
+ },
+ .ddr4 = {
+ .dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
+ .dq1 = { 1, 0, 5, 4, 6, 2, 3, 7, }, /* DDR4_DQ1[7:0] */
+ },
+ .ddr5 = {
+ .dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
+ .dq1 = { 0, 7, 2, 6, 3, 1, 4, 5, }, /* DDR5_DQ1[7:0] */
+ },
+ .ddr6 = {
+ .dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
+ .dq1 = { 4, 0, 5, 6, 3, 2, 1, 7, }, /* DDR6_DQ1[7:0] */
+ },
+ .ddr7 = {
+ .dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
+ .dq1 = { 7, 1, 2, 3, 6, 0, 5, 4, }, /* DDR7_DQ1[7:0] */
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .lpx_dqs_map = {
+ .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
+ },
+
+ .ect = true, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_ULT_ULX,
+};
+
const struct mb_cfg *variant_memory_params(void)
{
int board_id = get_board_id();
@@ -177,6 +233,8 @@ const struct mb_cfg *variant_memory_params(void)
case ADL_P_LP5_1:
case ADL_P_LP5_2:
return &lp5_mem_config;
+ case ADL_M_LP4:
+ return &adlm_lp4_mem_config;
default:
die("unsupported board id : 0x%x\n", board_id);
}
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 6ae5c17610..7e2638936d 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -59,6 +59,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
case ADL_P_LP4_2:
case ADL_P_LP5_1:
case ADL_P_LP5_2:
+ case ADL_M_LP4:
memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
break;
default:
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
index 6e6709fd7c..945e3eb347 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -1,10 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-only
-SPD_SOURCES = adlrvp_lp4 # 0b000
-SPD_SOURCES += empty # 0b001
-SPD_SOURCES += empty # 0b002
-SPD_SOURCES += adlrvp_lp5 # 0b003
-SPD_SOURCES += empty # 0b004
-SPD_SOURCES += empty # 0b005
-SPD_SOURCES += empty # 0b006
-SPD_SOURCES += adlrvp_lp5 # 0b007
+SPD_SOURCES = adlrvp_lp4 # 0b000
+SPD_SOURCES += adlrvp_m_lp4 # 0b001
+SPD_SOURCES += empty # 0b002
+SPD_SOURCES += adlrvp_lp5 # 0b003
+SPD_SOURCES += empty # 0b004
+SPD_SOURCES += empty # 0b005
+SPD_SOURCES += empty # 0b006
+SPD_SOURCES += adlrvp_lp5 # 0b007
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex
new file mode 100644
index 0000000000..4960258ff1
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_m_lp4.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 16 29 B9 08 00 40 00 00 02 01 00 00
+48 00 04 FF 92 54 05 00 8C 00 90 A8 90 E0 0B F0
+05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 04:14:37 +0000